Datasheet > GVT71128D32T-7I

GVT71128D32T-7I

更新时间： 2024-10-29 20:23:51

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器内存集成电路
页数	文件大小	规格书
13页	54K
描述
Standard SRAM, 128KX32, 7ns, CMOS, PQFP100, TQFP-100

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GVT71128D32T-7I 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LQFP,	针数：	100
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.84
Is Samacsys：	N	最长访问时间：	7 ns
JESD-30 代码：	R-PQFP-G100	长度：	20 mm
内存密度：	4194304 bit	内存集成电路类型：	STANDARD SRAM
内存宽度：	32	功能数量：	1
端子数量：	100	字数：	131072 words
字数代码：	128000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	128KX32	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装形状：	RECTANGULAR
封装形式：	FLATPACK	并行/串行：	PARALLEL
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3.1 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	宽度：	14 mm
Base Number Matches：	1

GVT71128D32T-7I 数据手册

GVT71128D32

128K X 32 SYNCHRONOUS BURST SRAM

GALVANTECH

SYNCHRONOUS

BURST SRAM

PIPELINED OUTPUT

128K x 32 SRAM

+3.3V SUPPLY, PIPELINED, SINGLE

CYCLE DESELECT, BURST COUNTER

FEATURES

GENERAL DESCRIPTION

•

Fast access times: 4.8, 5, 6, and 7ns

The Galvantech Synchronous Burst SRAM family

employs high-speed, low power CMOS designs using

advanced triple-layer polysilicon, double-layer metal

technology. Each memory cell consists of four transistors and

two high valued resistors.

The GVT71128D32 SRAM integrates 131,072x32

SRAM cells with advanced synchronous peripheral circuitry

and a 2-bit counter for internal burst operation. All

synchronous inputs are gated by registers controlled by a

positive-edge-triggered clock input (CLK). The synchronous

inputs include all addresses, all data inputs, address-pipelining

chip enable (CE#), depth-expansion chip enables (CE2# and

CE2), burst control inputs (ADSC#, ADSP#, and ADV#),

write enables (BW1#, BW2#, BW3#, BW4#,and BWE#), and

global write (GW#).

Asynchronous inputs include the output enable (OE#)

and burst mode control (MODE). The data outputs (Q),

enabled by OE#, are also asynchronous.

Addresses and chip enables are registered with either

address status processor (ADSP#) or address status controller

(ADSC#) input pins. Subsequent burst addresses can be

internally generated as controlled by the burst advance pin

(ADV#).

Fast clock speed: 100, 83, and 66MHz

Provide high performance 3-1-1-1 access rate

Fast OE# access times: 5, 6, and 7ns

Optimal for depth expansion (one cycle chip deselect to

eliminate bus contention)

Single +3.3V -5% and +10%power supply

Support +2.5V I/O

5V tolerant inputs except I/O’s

Clamp diodes to VSSQ at all outputs

Common data inputs and data outputs

BYTE WRITE ENABLE and GLOBAL WRITE control

Three chip enables for depth expansion and address

pipeline

Address, control, input, and output pipeline registers

Internally self-timed WRITE CYCLE

Burst control pins (interleaved or linear burst sequence)

Automatic power-down for portable applications

High density, high speed packages

•

Low capacitive bus loading

High 30pF output drive capability at rated access time

OPTIONS

•

MARKING

Timing

Address, data inputs, and write controls are registered on-

chip to initiate self-timed WRITE cycle. WRITE cycles can

be one to four bytes wide as controlled by the write control

inputs. Individual byte write allows individual byte to be

written. BW1# controls DQ1-DQ8. BW2# controls DQ9-

DQ16. BW3# controls DQ17-DQ24. BW4# controls DQ25-

DQ32. BW1#, BW2# BW3#, and BW4# can be active only

with BWE# being LOW. GW# being LOW causes all bytes to

be written. This device also incorporates pipelined enable

circuit for easy depth expansion without penalizing system

performance.

4.8ns access/10ns cycle

5ns access/10ns cycle

6ns access/12ns cycle

7ns access/15ns cycle

-4

-5

-6

-7

•

Packages

100-pin TQFP

Temperature

Commercial

Industrial

None (0°C to 70°C)

(-40°C to 85°C)

The GVT71128D32 operates from a +3.3V power

supply. All inputs and outputs are TTL-compatible. The

device is ideally suited for 486, Pentium , 680x0, and

PowerPC systems and for systems that are benefited from a

wide synchronous data bus.

Pentium is a trademark of Intel Corporation.

PowerPC is a trademark of IBM Corporation.

Galvantech, Inc. reserves the right to change

products or specifications without notice.

Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051

Tel (408) 566-0688 Fax (408) 566-0699 Web Site www.galvantech.com

Rev. 11/99

12 3 4 5 6 7...13

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与GVT71128D32T-7I相关器件

型号	品牌	获取价格	描述	数据表
GVT71128DA36B-4	ETC	获取价格	x36 Fast Synchronous SRAM
GVT71128DA36B-4.4	ETC	获取价格	x36 Fast Synchronous SRAM
GVT71128DA36B-5	ETC	获取价格	x36 Fast Synchronous SRAM
GVT71128DA36B-6	CYPRESS	获取价格	Cache SRAM, 128KX36, 3.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, LOW PROFILE, FBGA-1
GVT71128DA36T-4	ETC	获取价格	x36 Fast Synchronous SRAM
GVT71128DA36T-4.4	ETC	获取价格	x36 Fast Synchronous SRAM
GVT71128DA36T-5	CYPRESS	获取价格	Cache SRAM, 128KX36, 2.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
GVT71128DA36T-6	CYPRESS	获取价格	Cache SRAM, 128KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
GVT71128E36B-10	ETC	获取价格	x36 Fast Synchronous SRAM
GVT71128E36B-7	CYPRESS	获取价格	Standard SRAM, 128KX36, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119

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