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GVT71128DA36B-6

更新时间： 2023-12-18 00:00:00
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟静态存储器内存集成电路
页数 文件大小 规格书
24页 290K
描述
Cache SRAM, 128KX36, 3.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, LOW PROFILE, FBGA-119

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GVT71128DA36B-6 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：14 X 22 MM, 2.40 MM HEIGHT, LOW PROFILE, FBGA-119
针数：119Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.92最长访问时间：3.5 ns
最大时钟频率 (fCLK)：166 MHzI/O 类型：COMMON
JESD-30 代码：R-PBGA-B119JESD-609代码：e0
长度：22 mm内存密度：4718592 bit
内存集成电路类型：CACHE SRAM内存宽度：36
功能数量：1端子数量：119
字数：131072 words字数代码：128000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：128KX36
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA119,7X17,50
封装形状：RECTANGULAR封装形式：GRID ARRAY
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V认证状态：Not Qualified
座面最大高度：2.4 mm最大待机电流：0.01 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.3 mA最大供电电压 (Vsup)：3.63 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1.27 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

GVT71128DA36B-6 数据手册

 浏览型号GVT71128DA36B-6的Datasheet PDF文件第2页浏览型号GVT71128DA36B-6的Datasheet PDF文件第3页浏览型号GVT71128DA36B-6的Datasheet PDF文件第4页浏览型号GVT71128DA36B-6的Datasheet PDF文件第5页浏览型号GVT71128DA36B-6的Datasheet PDF文件第6页浏览型号GVT71128DA36B-6的Datasheet PDF文件第7页 
CY7C1347C/GVT71128DA36  
CY7C1327C/GVT71256DA18  
256K x 18/128K x 36 Synchronous-Pipelined  
Cache RAM  
The CY7C1347C/GVT71128DA36 and CYC7C1327C/  
GVT71256DA18 SRAMs integrate 131,072x36 and  
262,144x18 SRAM cells with advanced synchronous periph-  
Features  
• Fast access times: 2.5 and 3.5 ns  
eral circuitry and a 2-bit counter for internal burst operation. All  
synchronous inputs are gated by registers controlled by a pos-  
itive-edge-triggered clock input (CLK). The synchronous in-  
puts include all addresses, all data inputs, address-pipelining  
Chip Enable (CE), depth-expansion Chip Enables (CE2 and  
CE2), Burst Control Inputs (ADSC, ADSP, and ADV), Write  
Enables (BWa, BWb, BWc, BWd, and BWE), and Global Write  
(GW).  
• Fast clock speed: 250, 225, 200, and 166 MHz  
• 1-ns set-up time and hold time  
• Fast OE access times: 2.5 ns and 3.5 ns  
• Optimal for depth expansion (one cycle chip deselect  
to eliminate bus contention)  
• 3.3V –5% and +10% power supply  
• 3.3V or 2.5V I/O supply  
• 5V tolerant inputs except I/Os  
Asynchronous inputs include the Output Enable (OE) and  
Burst Mode Control (MODE). The data outputs (Q), enabled  
by OE, are also asynchronous.  
• Clamp diodes to V at all inputs and outputs  
SS  
• Common data inputs and data outputs  
Addresses and chip enables are registered with either Ad-  
dress Status Processor (ADSP) or Address Status Controller  
(ADSC) input pins. Subsequent burst addresses can be inter-  
nally generated as controlled by the Burst Advance pin (ADV).  
• Byte Write Enable and Global Write control  
• Three chip enables for depth expansion and address  
pipeline  
• Address, data, and control registers  
• Internally self-timed Write Cycle  
• Burst control pins (interleaved or linear burst se-  
quence)  
• Automatic power-down for portable applications  
• JTAG boundary scan  
• JEDEC standard pinout  
• Low profile 119-lead, 14-mm x 22-mm BGA (Ball Grid  
Array) and 100-pin TQFP packages  
Address, data inputs, and write controls are registered on-chip  
to initiate self-timed Write cycle. Write cycles can be one to  
four bytes wide as controlled by the write control inputs. Indi-  
vidual byte write allows individual byte to be written. BWa con-  
trols DQa. BWb controls DQb. BWc controls DQc. BWd con-  
trols DQd. BWa, BWb, BWc, and BWd can be active only with  
BWE being LOW. GW being LOW causes all bytes to be writ-  
ten. The x18 version only has 18 data inputs/outputs (DQa and  
DQb) along with BWa and BWb (no BWc, BWd, DQc, and  
DQd).  
Functional Description  
Four pins are used to implement JTAG test capabilities: Test  
Mode Select (TMS), Test Data-in (TDI), Test Clock (TCK), and  
Test Data-out (TDO). The JTAG circuitry is used to serially shift  
data to and from the device. JTAG inputs use LVTTL/LVCMOS  
levels to shift data during this testing mode of operation.  
The Cypress Synchronous Burst SRAM family employs  
high-speed, low-power CMOS designs using advanced tri-  
ple-layer polysilicon, double-layer metal technology. Each  
memory cell consists of four transistors and two high-valued  
resistors.  
The  
CY7C1347C/GVT71128DA36  
and  
CY7C1327C/  
GVT71256DA18 operate from a +3.3V power supply. All inputs  
and outputs are LVTTL compatible  
Selection Guide  
7C1347C-250  
7C1347C-225  
71128DA36-4.4  
7C1327C-225  
71256DA18-4.4  
7C1347C-200  
71128DA36-5  
7C1327C-200  
71256DA18-5  
7C1347C-166  
71128DA36-6  
7C1327C-166  
71256DA18-6  
71128DA36-4  
7C1327C-250  
71256DA18-4  
Maximum Access Time (ns)  
2.5  
450  
10  
2.5  
400  
10  
2.5  
360  
10  
3.5  
300  
10  
Maximum Operating Current (mA)  
Maximum CMOS Standby Current (mA)  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
July 21, 2000  
1234567...24

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GVT71128DA36T-4 ETC

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GVT71128DA36T-4.4 ETC

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 		x36 Fast Synchronous SRAM
GVT71128DA36T-5 CYPRESS

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 		Cache SRAM, 128KX36, 2.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
GVT71128DA36T-6 CYPRESS

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 		Cache SRAM, 128KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
GVT71128E36B-10 ETC

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 		x36 Fast Synchronous SRAM
GVT71128E36B-7 CYPRESS

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 		Standard SRAM, 128KX36, 7.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119
GVT71128E36B-8 CYPRESS

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 		Standard SRAM, 128KX36, 8ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, FBGA-119
GVT71128E36B-9 ETC

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 		x36 Fast Synchronous SRAM
GVT71128E36T-10 ETC

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 		x36 Fast Synchronous SRAM
GVT71128E36T-7 CYPRESS

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 		Standard SRAM, 128KX36, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-10

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