CY7C1347A/GVT71128G36
128K x 36 Synchronous Pipelined Burst SRAM
eral circuitry and a 2-bit counter for internal burst operation. All
synchronous inputs are gated by registers controlled by a pos-
Features
• Fast access times: 3.5, 3.8, and 4.0 ns
itive-edge-triggered Clock Input (CLK). The synchronous in-
puts include all addresses, all data inputs, address-pipelining
Chip Enable (CE), depth-expansion Chip Enables (CE2 and
CE2), Burst Control inputs (ADSC, ADSP, and ADV), Write
Enables (BW1, BW2, BW3, BW4, and BWE), and Global Write
(GW).
• Fast clock speed: 166, 150, 133, and 117 MHz
• Provide high-performance 3-1-1-1 access rate
• Fast OE access times: 3.5 ns and 3.8 ns
• Optimal for depth expansion (one cycle chip deselect
to eliminate bus contention)
• 3.3V –5% and +10% power supply
• 2.5V or 3.3V I/O supply
• 5V tolerant inputs except I/Os
Asynchronous inputs include the Output Enable (OE) and
Burst Mode Control (MODE). The data outputs (Q), enabled
by OE, are also asynchronous.
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance pin (ADV).
• Clamp diodes to VSSQ at all inputs and outputs
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
• Three chip enables for depth expansion and address
pipeline
• Address, data, and control registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst se-
quence)
• Automatic power-down for portable applications
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle. Write cycles can be one to
four bytes wide as controlled by the write control inputs. Indi-
vidual byte write allows individual byte to be written. BW1 con-
trols DQ1–DQ8 and DQP1. BW2 controls DQ9–DQ16 and
DQP2. BW3 controls DQ17–DQ24 and DQP3. BW4 controls
DQ25–DQ32 and DQP4. BW1, BW2, BW3, and BW4 can be
active only with BWE being LOW. GW being LOW causes all
bytes to be written. Write pass-through capability allows writ-
ten data available at the output for the immediately next Read
cycle. This device also incorporates pipelined enable circuit for
easy depth expansion without penalizing system performance.
• Low profile 119-lead, 14-mm x 22-mm BGA (Ball Grid
Array) and 100-pin TQFP packages
Functional Description
The Cypress Synchronous Burst SRAM family employs high-
speed, low-power CMOS designs using advanced triple-layer
polysilicon, double-layer metal technology. Each memory cell
consists of four transistors and two high-valued resistors.
The CY7C1347A/GVT71128G36 operates from a +3.3V pow-
er supply and all outputs operate on a +2.5V supply. All inputs
and outputs are JEDEC standard JESD8-5 compatible. The
device is ideally suited for 486, Pentium®, 680x0, and Power-
PC™ systems and for systems that benefit from a wide syn-
chronous data bus.
The
CY7C1347A/GVT71128G36
SRAM
integrates
131,072x36 SRAM cells with advanced synchronous periph-
Selection Guide
7C1347A-166
71128G36-3
7C1347A-150
71128G36-4
7C1347A-133
71128G36-5
7C1347A-117
71128G36-6
Maximum Access Time (ns)
3.5
425
10
3.8
400
10
4.0
375
10
4.0
350
10
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Cypress Semiconductor Corporation
Document #: 38-05128 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised November 13, 2002