GS88037BT-333/300/250/200
333 MHz–200 MHz
100-Pin TQFP
Commercial Temp
Industrial Temp
256K x 36
9Mb Sync Burst SRAM
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Features
• Single Cycle Deselect (SCD) operation
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
SCD Pipelined Reads
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
The GS88037BT is a SCD (Single Cycle Deselect) pipelined
synchronous SRAM. DCD (Dual Cycle Deselect) versions are
also available. SCD SRAMs pipeline deselect commands one
stage less than read commands. SCD RAMs begin turning off
their outputs immediately after the deselect command has been
captured in the input registers.
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
• Pb-Free 100-lead TQFP package available
Functional Description
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Applications
The GS88037BT is a 9,437,184-bit (8,388,608-bit for x32
version) high performance synchronous SRAM with a
2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main
store to networking chip set support.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Core and Interface Voltages
The GS88037BT operates on a 2.5 V or 3.3 V power supply.
All input are 3.3 V and 2.5 V compatible. Separate output
power (V
) pins are used to decouple output noise from the
DDQ
internal circuits and are 3.3 V and 2.5 V compatible.
Parameter Synopsis
-333
-300
-250
-200
Unit
Pipeline
3-1-1-1
t
2.0
3.0
2.2
3.3
2.3
4.0
2.7
5.0
ns
ns
KQ
tCycle
3.3 V
2.5 V
Curr (x36)
Curr (x36)
435
435
395
395
330
330
270
270
mA
mA
Rev: 1.04 2/2005
1/19
© 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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