Datasheet > GS88037BT-150IT

GS88037BT-150IT

更新时间： 2024-11-08 14:42:23

品牌	Logo	应用领域
GSI		静态存储器
页数	文件大小	规格书
19页	573K
描述
SRAM

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技术参数
数据手册

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GS88037BT-150IT 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	,	Reach Compliance Code：	unknown
风险等级：	5.92	湿度敏感等级：	3
Base Number Matches：	1

GS88037BT-150IT 数据手册

Preliminary

GS88037BT-333/300/275/250/225/200

100-Pin TQFP

Commercial Temp

Industrial Temp

333 MHz–200 MHz

256K x 36

9Mb Sync Burst SRAM

2.5 V or 3.3 V V_DD

2.5 V or 3.3 V I/O

stage less than read commands. SCD RAMs begin turning off

their outputs immediately after the deselect command has been

captured in the input registers.

Features

• Single Cycle Deselect (SCD) operation

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP package

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

-333 -300 -275 -250 -225 -200 Unit

Pipeline

3-1-1-1

2.0 2.2 2.3 2.3 2.5 2.7 ns

3.0 3.3 3.6 4.0 4.4 5.0 ns

Core and Interface Voltages

tCycle

The GS88037BT operates on a 2.5 V or 3.3 V power supply.

3.3 V

2.5 V

Curr (x36) 435 395 360 330 300 270 mA

All input are 3.3 V and 2.5 V compatible. Separate output

power (V

) pins are used to decouple output noise from the

DDQ

internal circuits and are 3.3 V and 2.5 V compatible.

Functional Description

Applications

The GS88037BT is a 9,437,184-bit (8,388,608-bit for x32

version) high performance synchronous SRAM with a

2-bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPUs, the device now finds application in

synchronous SRAM applications, ranging from DSP main

store to networking chip set support.

Controls

Addresses, data I/Os, chip enables (E1, E2, E3), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

SCD Pipelined Reads

The GS88037BT is a SCD (Single Cycle Deselect) pipelined

synchronous SRAM. DCD (Dual Cycle Deselect) versions are

also available. SCD SRAMs pipeline deselect commands one

Rev: 1.00b 12/2002

1/19

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

12 3 4 5 6 7...19

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与GS88037BT-150IT相关器件

型号	品牌	获取价格	描述	数据表
GS88037BT-150T	GSI	获取价格	SRAM
GS88037BT-166I	GSI	获取价格	SRAM
GS88037BT-166T	GSI	获取价格	SRAM
GS88037BT-200	GSI	获取价格	256K x 36 9Mb Sync Burst SRAM
GS88037BT-200I	GSI	获取价格	256K x 36 9Mb Sync Burst SRAM
GS88037BT-200IV	GSI	获取价格	256K x 36 9Mb Sync Burst SRAM
GS88037BT-200IVT	GSI	获取价格	Cache SRAM, 256KX36, 2.5ns, CMOS, PQFP100, TQFP-100
GS88037BT-200T	GSI	获取价格	暂无描述
GS88037BT-200V	GSI	获取价格	256K x 36 9Mb Sync Burst SRAM
GS88037BT-200VT	GSI	获取价格	Cache SRAM, 256KX36, 2.5ns, CMOS, PQFP100, TQFP-100

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