2.5 Gbit/s
Clock and Data
Recovery and
1:16 DeMUX
GD16524
an Intel company
General Description
Features
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The GD16524 is a high performance
monolithic integrated multi-rate Clock
and Data Recovery (CDR) device appli-
cable for optical communication systems
including:
The CDR contains all circuits needed for
reliable acquisition and lock of the VCO
phase to the incoming data-stream.
The electrical input sensitivity is better
than 8 mV (BER <10-10).
Exceeds ITU-T and Bellcore require-
ments of Jitter Transfer, Generation
and Tolerance.
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Integrated Limiting amplifier.
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SDH STM-16 / 4 / 1
SONET OC-48 / 12 / 3
Gigabit Ethernet
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The device exceeds all ITU-T and
Bellcore IEEE jitter requirements when
used with the recommended loop filter,
according to Figure 3 (jitter tolerance,
-transfer and -generation).
On-the-fly multi-bit-rate operation
7% overhead data rate capability.
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The GD16524 features:
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Digital LOS monitor and alarm output.
Limiting input amplifier.
Analogue peak level detection circuit.
Digital Loss Of Signal (LOS) monitor
circuit with four selectable threshold
settings.
Consecutive Identical Binary Digit
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Bit Consecutive Detect output.
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The output clock (2.488 GHz when
STM-16 data input is selected) is main-
tained within 500 ppm tolerance of the
reference frequency in the absence of
data.
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Multi-rate data input.
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Differential CML data input with
internal 50 W load termination.
alarm output.
1:16 de-multiplexer.
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The integrated 1:16 de-multiplexer with
differential LVPECL outputs provides a
simple interface to system ASICs.
Integrated 1:16 DeMUX with LVPECL
outputs.
GD16524 can be switched “on-the-fly” to
and from 2.488 Gbit/s, 1.244 Gbit/s,
622.08 Mbit/s, and 155.52 Mbit/s.
GD16524 also supports up to 7% over-
head, allowing for 2.66 Gbit/s data
transfer.
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Control inputs are LVTTL.
The GD16524 is available in a 100 pin
TQFP package (14 × 14 mm) with heat
slug on bottom surface.
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Reference clock selectable:
–
–
155.52 MHz
38.88 MHz
The device also features an additional
high-speed data input for serial loop-back
diagnostic tests.
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High-speed serial loop-back input.
Single supply operation: +3.3 V
Power dissipation: 800 mW (typ.)
DEC_ADJ SD_SEL
TCK
VCTL
BRS0 BRS1
SELTCK
MON
Peak
Detect
PCOP
PCON
Divider
Available in a 100 pin TQFP package
(14 × 14 mm) with heat slug on
bottom surface.
MON_REF
VCO
DO0
DON0
SDIP
DIREF
B.B
Phase
Detector
MUX
SDIN
DIREFN
Limiting
Amplifier
DO15
DON15
Applications
VCC
VCCL
VCCO
VCCP
VCCV
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Clock and Data Recovery for optical
communication systems including:
Continuous
Bit
Detector
SLBIP
SLBIN
Lock
Detect
BC_DET
BER
–
–
–
SDH STM-16
SONET OC-48
Gigabit Ethernet
Amplifier
LOCK_DET
SBER0
SBER1
LOCK
LOS_DET
/ 4
VBB
Phase
Frequency
Detect
MUX
PCTL
RCIP
RCIN
VEE
VEEL
VEEP
VEEV
REF_SEL
CDR_SEL
Data Sheet Rev.: 26