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GD16524-100BA PDF预览

GD16524-100BA

更新时间: 2024-01-08 18:04:48
品牌 Logo 应用领域
其他 - ETC 电信集成电路异步传输模式ATM时钟
页数 文件大小 规格书
13页 132K
描述
CLOCK/DATA RECOVERY|QFP|100PIN|PLASTIC

GD16524-100BA 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:HLFQFP, HQFP100,.63SQ,20针数:100
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.84应用程序:SONET;SDH
JESD-30 代码:S-PQFP-G100长度:14 mm
功能数量:1端子数量:100
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:HLFQFP
封装等效代码:HQFP100,.63SQ,20封装形状:SQUARE
封装形式:FLATPACK, HEAT SINK/SLUG, LOW PROFILE, FINE PITCH电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
子类别:ATM/SONET/SDH ICs最大压摆率:0.2 mA
标称供电电压:3.3 V表面贴装:YES
电信集成电路类型:ATM/SONET/SDH CLOCK RECOVERY CIRCUIT温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD宽度:14 mm
Base Number Matches:1

GD16524-100BA 数据手册

 浏览型号GD16524-100BA的Datasheet PDF文件第2页浏览型号GD16524-100BA的Datasheet PDF文件第3页浏览型号GD16524-100BA的Datasheet PDF文件第4页浏览型号GD16524-100BA的Datasheet PDF文件第5页浏览型号GD16524-100BA的Datasheet PDF文件第6页浏览型号GD16524-100BA的Datasheet PDF文件第7页 
2.5 Gbit/s  
Clock and Data  
Recovery and  
1:16 DeMUX  
GD16524  
an Intel company  
General Description  
Features  
l
The GD16524 is a high performance  
monolithic integrated multi-rate Clock  
and Data Recovery (CDR) device appli-  
cable for optical communication systems  
including:  
The CDR contains all circuits needed for  
reliable acquisition and lock of the VCO  
phase to the incoming data-stream.  
The electrical input sensitivity is better  
than 8 mV (BER <10-10).  
Exceeds ITU-T and Bellcore require-  
ments of Jitter Transfer, Generation  
and Tolerance.  
l
Integrated Limiting amplifier.  
u
SDH STM-16 / 4 / 1  
SONET OC-48 / 12 / 3  
Gigabit Ethernet  
l
u
The device exceeds all ITU-T and  
Bellcore IEEE jitter requirements when  
used with the recommended loop filter,  
according to Figure 3 (jitter tolerance,  
-transfer and -generation).  
On-the-fly multi-bit-rate operation  
7% overhead data rate capability.  
u
l
The GD16524 features:  
u
Digital LOS monitor and alarm output.  
Limiting input amplifier.  
Analogue peak level detection circuit.  
Digital Loss Of Signal (LOS) monitor  
circuit with four selectable threshold  
settings.  
Consecutive Identical Binary Digit  
l
u
Bit Consecutive Detect output.  
u
The output clock (2.488 GHz when  
STM-16 data input is selected) is main-  
tained within 500 ppm tolerance of the  
reference frequency in the absence of  
data.  
l
Multi-rate data input.  
l
u
Differential CML data input with  
internal 50 W load termination.  
alarm output.  
1:16 de-multiplexer.  
u
l
The integrated 1:16 de-multiplexer with  
differential LVPECL outputs provides a  
simple interface to system ASICs.  
Integrated 1:16 DeMUX with LVPECL  
outputs.  
GD16524 can be switched “on-the-fly” to  
and from 2.488 Gbit/s, 1.244 Gbit/s,  
622.08 Mbit/s, and 155.52 Mbit/s.  
GD16524 also supports up to 7% over-  
head, allowing for 2.66 Gbit/s data  
transfer.  
l
Control inputs are LVTTL.  
The GD16524 is available in a 100 pin  
TQFP package (14 × 14 mm) with heat  
slug on bottom surface.  
l
Reference clock selectable:  
155.52 MHz  
38.88 MHz  
The device also features an additional  
high-speed data input for serial loop-back  
diagnostic tests.  
l
l
l
l
High-speed serial loop-back input.  
Single supply operation: +3.3 V  
Power dissipation: 800 mW (typ.)  
DEC_ADJ SD_SEL  
TCK  
VCTL  
BRS0 BRS1  
SELTCK  
MON  
Peak  
Detect  
PCOP  
PCON  
Divider  
Available in a 100 pin TQFP package  
(14 × 14 mm) with heat slug on  
bottom surface.  
MON_REF  
VCO  
DO0  
DON0  
SDIP  
DIREF  
B.B  
Phase  
Detector  
MUX  
SDIN  
DIREFN  
Limiting  
Amplifier  
DO15  
DON15  
Applications  
VCC  
VCCL  
VCCO  
VCCP  
VCCV  
l
Clock and Data Recovery for optical  
communication systems including:  
Continuous  
Bit  
Detector  
SLBIP  
SLBIN  
Lock  
Detect  
BC_DET  
BER  
SDH STM-16  
SONET OC-48  
Gigabit Ethernet  
Amplifier  
LOCK_DET  
SBER0  
SBER1  
LOCK  
LOS_DET  
/ 4  
VBB  
Phase  
Frequency  
Detect  
MUX  
PCTL  
RCIP  
RCIN  
VEE  
VEEL  
VEEP  
VEEV  
REF_SEL  
CDR_SEL  
Data Sheet Rev.: 26  

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