Datasheet > GD16522-48BA

GD16522-48BA

更新时间： 2022-01-19 15:04:00

品牌	Logo	应用领域
其他 - ETC		时钟
页数	文件大小	规格书
12页	146K
描述
CLOCK/DATA RECOVERY\|BIPOLAR\|QFP\|48PIN\|PLASTIC

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GD16522-48BA 数据手册

2.5 Gbit/s

Clock and Data

Recovery

GD16522

an Intel company

General Description

Features

The GD16522 is a high performance

monolithic integrated multi-rate Clock

and Data Recovery (CDR) device appli-

cable for optical communication systems

including:

The CDR contains all circuits needed for

reliable acquisition and lock of the VCO

phase to the incoming data-stream.

Exceeds ITU-T and Bellcore require-

ments of Jitter Transfer, Generation

and Tolerance.

The electrical input sensitivity is better

than 8 mV (BER <10^-10).

Integrated Limiting Amplifier.

SDH STM-16 / 4 / 1

SONET OC-48 / 12 / 3

Gigabit Ethernet

Digital LOS monitor and alarm output.

The device exceeds all ITU-T and

Bellcore IEEE jitter requirements when

used with the recommended loop filter

(jitter tolerance, -transfer and -genera-

tion).

Bit Consecutive Detect Output.

The GD16522 features:

Limiting input amplifier.

Analogue peak level detection circuit.

Digital Loss Of Signal (LOS) monitor

Multi-rate data input.

Differential CML data input with inter-

nal 50 W load termination.

circuit with four selectable threshold

settings.

Consecutive Identical Binary Digit

The output clock (2.488 GHz when

STM-16 data input is selected) is main-

tained within 500 ppm tolerance of the

reference frequency in the absence of

data.

Control inputs are LVTTL.

alarm output.

Reference clock selectable:

The device also features an additional

high-speed data input for serial loop-back

diagnostic tests.

–

155.52 MHz

38.88 MHz

The GD16522 is available in 48 lead

7 × 7 mm TQFP power enhanced plastic

package.

Single supply operation: +3.3 V.

High-speed serial loop-back input.

Output signal shutdown input.

DEC_ADJ SD_SEL

TCK

VCTL

BRS0 BRS1

SELTCK

VCC

Available in 48 pin TQFP package

(7 × 7 mm).

VCCL

VCCO

VCCP

VCCV

MON

Peak

Detect

Divider

MON_REF

VCO

SDIP

DIREF

SCOP

SCON

SDOP

SDON

B.B

Phase

Detector

Applications

MUX

SDIN

DIREFN

Limiting

Amplifier

Clock and Data Recovery for optical

communication systems including:

SDOWN_G

SDOWN_L

–

SDH STM-16 / 4 / 1

SONET OC-48 / 12 / 3

Gigabit Ethernet

Continuous

Bit

Detector

SLBIP

SLBIN

Lock

Detect

BC_DET

BEF

Amplifier

LOCK_DET

LOS_DET

SBER0

SBER1

Phase

Frequency

Detect

1/4

MUX

PCTL

RCIP

RCIN

VEE

VEEL

VEEP

VEEV

REF_SEL

CDR_SEL

Data Sheet Rev.: 21

12 3 4 5 6 7...12

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