Datasheet > GD16505-68BA

GD16505-68BA

更新时间： 2024-01-13 10:35:39

品牌	Logo	应用领域
英特尔 - INTEL		ATM 异步传输模式信息通信管理
页数	文件大小	规格书
8页	445K
描述
Mux/Demux, 1-Func, BICMOS, CQFP68, MLC-68

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技术参数
数据手册

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GD16505-68BA 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	QFP, QFP68,.85SQ,40	针数：	68
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.84	应用程序：	SONET;SDH
JESD-30 代码：	S-CQFP-G68	长度：	19.05 mm
负电源额定电压：	-5 V	功能数量：	1
端子数量：	68	最高工作温度：	85 °C
最低工作温度：		封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	QFP	封装等效代码：	QFP68,.85SQ,40
封装形状：	SQUARE	封装形式：	FLATPACK
电源：	-5.2 V	认证状态：	Not Qualified
座面最大高度：	3.302 mm	子类别：	ATM/SONET/SDH ICs
最大压摆率：	0.25 mA	表面贴装：	YES
技术：	BICMOS	电信集成电路类型：	ATM/SONET/SDH MUX/DEMUX
温度等级：	OTHER	端子形式：	GULL WING
端子节距：	1.016 mm	端子位置：	QUAD
宽度：	19.05 mm	Base Number Matches：	1

GD16505-68BA 数据手册

Functional Details

Application Details

The GD16505 consists of 3 major func-

tional parts:

a 16:1 MUX unit

PLL Loop Filter and

PLL Reset

The op-amp must be able to drive the

IODC pin input in the range V -2.0 V to

+1.2 V.

a PLL (PFD) system

a laser driver.

The recommended loop filter for the

GD16505 is shown in Figure 2. This loop

filter is used in the AC production test

set-up and has been found to ensure that

the jitter performance of GD16505 is

within ITU specifications.

GD16505-68BA

The function of the MUX is to multiplex

the 16-bit word DIx0-DIx15 into a 16-bit

serial-data stream. The order of bits in

the multiplexed bit stream is DIx15 as the

first coming bit and then DIx14, …, DIx1,

and DIx0.

The GD16505-BA version is made to

give the old customers of GD16055 a

plug compatible silicon device with im-

proved AC and DC.

The optimum choice of component

values with regard to jitter is affected by

the reference clock phase-noise perfor-

mance.

The 68 lead MLC package sets some

limitation to the functionality of the de-

vice.

The multiplexed bit stream is buffered

and converted to an output current in the

laser driver in order to interface to a

25 Ω/50 Ω laser diode (or external im-

pedance). Logic HI means output current

in pin SON (i.e. laser on for 50 Ω laser

diode interface) and output current in pin

SOP LO (i.e. laser off for 25 Ω laser

diode interface).

For noise and jitter reasons it is very im-

portant that the capacitor is connected to

VDD/VDDA close to VCTL pin.

Also the limited number of pins has re-

duced the selectable reference clock,

hence only 155.52 MHz is available.

Lock Detect Circuit

On GD16505-68BA, the laser driver is

coupled as a CML output, i.e. the polarity

is a high voltage on SOP for logic high,

also current specifications have been re-

duced to 30 mA in 50 Ω. And all special

control inputs on the laser driver have

been removed leaving only IODC for

controlling the output current.

A simple PLL lock detect function can be

implemented by 3 external components

(R3, C3 and ST1), comprising a low-pass

filter followed by a Schmitt trigger, as

shown in Figure 2.

On GD16505-68BA, the laser driver is

coupled as a CML output, i.e. Logic HI

means High voltage on pin SOP.

50Ω

SON / 58

SOP / 59

50Ω

NLDET / 6

PFCO / 3

ST1

LOCK

PFC

2k2

10nF

VCO

IODC / 57

VCTL / 2

VEE

*: I

= 80/3 × I

IODC

SOP/SON

Figure 2. PLL Loop Filter (68BA)

Figure 1. CML Output (68BA)

The PLL system consists of a low-jitter

LC type VCO running at approximately

2.5 GHz, an analog phase/frequency de-

tector and a charge pump.

Laser Driver Current Control

The output modulation current is con-

trolled by the pin IODC and can be con-

trolled in the range from 5 mA to 80 mA.

The 2.5 GHz VCO, is locked to an exter-

nal reference clock selectable at

155.52 MHz or 77.6 MHz.

The output voltage swing across the ex-

ternal load may be varied accordingly.

The modulation current control on pin

IODC is implemented as a current mirror

and therefore sinks a current proportional

to the modulation current. The current

sink into the IODC pin is 3/80 of the

modulation current.

The 16:1 MUX can be bypassed by set-

ting the SEL4 input high, thus selecting

the 2.5 Gbit/s ECL inputs SIP / SIN.

By using an external general-purpose

operational amplifier the laser current

may be controlled accurately and inde-

pendent of environmental changes.

Data Sheet Rev. 04

GD16505

Page 2

123 4 5 6 7 8

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与GD16505-68BA相关器件

型号	品牌	描述	获取价格	数据表
GD16506-144EA	INTEL	Clock Recovery Circuit, 1-Func, PBGA144, PLASTIC, FPBGA-144	获取价格
GD16506-68BA	INTEL	Clock Recovery Circuit, 1-Func, MLC-68	获取价格
GD16507-144EA	INTEL	Mux/Demux, 1-Func, BICMOS, PBGA144, FPBGA-144	获取价格
GD16507-68BA	INTEL	Mux/Demux, 1-Func, BICMOS, MLC-68	获取价格
GD16521	ETC	2.5 GBIT/S RE TIMING LASER DRIVER	获取价格
GD16521-48BA	INTEL	Support Circuit, 1-Func, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, HEAT SINK, PLASTIC, TQFP-48	获取价格

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