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GAL20V8B-7LPN

更新时间： 2024-12-01 04:19:15
品牌 Logo 应用领域
莱迪思 - LATTICE /
页数 文件大小 规格书
25页 578K
描述
High Performance E2CMOS PLD Generic Array Logic⑩

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GAL20V8B-7LPN 数据手册

 浏览型号GAL20V8B-7LPN的Datasheet PDF文件第2页浏览型号GAL20V8B-7LPN的Datasheet PDF文件第3页浏览型号GAL20V8B-7LPN的Datasheet PDF文件第4页浏览型号GAL20V8B-7LPN的Datasheet PDF文件第5页浏览型号GAL20V8B-7LPN的Datasheet PDF文件第6页浏览型号GAL20V8B-7LPN的Datasheet PDF文件第7页 
GAL20V8  
High Performance E2CMOS PLD  
Generic Array Logic™  
Features  
Functional Block Diagram  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
— 5 ns Maximum Propagation Delay  
— Fmax = 166 MHz  
I/CLK  
I
IMUX  
I
CLK  
— 4 ns Maximum from Clock Input to Data Output  
— UltraMOS® Advanced CMOS Technology  
I/O/Q  
8
8
OLMC  
I
I
I
I
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR  
— 75mA Typ Icc on Low Power Device  
— 45mA Typ Icc on Quarter Power Device  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
• ACTIVE PULL-UPS ON ALL PINS  
• E2 CELL TECHNOLOGY  
— Reconfigurable Logic  
— Reprogrammable Cells  
— 100% Tested/100% Yields  
— High Speed Electrical Erasure (<100ms)  
— 20 Year Data Retention  
8
8
8
• EIGHT OUTPUT LOGIC MACROCELLS  
— Maximum Flexibility for Complex Logic Designs  
— Programmable Output Polarity  
I
I
— Also Emulates 24-pin PAL® Devices with Full Function/  
Fuse Map/Parametric Compatibility  
8
8
8
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS  
— 100% Functional Testability  
I
• APPLICATIONS INCLUDE:  
— DMA Control  
— State Machine Control  
— High Speed Graphics Processing  
— Standard Logic Speed Upgrade  
OLMC  
IMUX  
I
I
OE  
I
I/OE  
• ELECTRONIC SIGNATURE FOR IDENTIFICATION  
• LEAD-FREE PACKAGE OPTIONS  
Description  
Pin Configuration  
The GAL20V8C, at 5ns maximum propagation delay time, com-  
bines a high performance CMOS process with Electrically Eras-  
able (E2) floating gate technology to provide the highest speed  
performance available in the PLD market. High speed erase times  
(<100ms) allow the devices to be reprogrammed quickly and ef-  
ficiently.  
DIP  
PLCC  
1
Vcc  
24  
I/CLK  
I
I
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I
I
I
I
I
GAL  
4
2
28  
26  
The generic architecture provides maximum design flexibility by  
allowing the Output Logic Macrocell (OLMC) to be configured by  
the user. An important subset of the many architecture configura-  
tions possible with the GAL20V8 are the PAL architectures listed  
in the table of the macrocell description section. GAL20V8 devices  
are capable of emulating any of these PAL architectures with full  
function/fuse map/parametric compatibility.  
20V8  
5
7
I
I
I
25 I/O/Q  
I/O/Q  
23  
6
I/O/Q  
NC  
GAL20V8  
Top View  
NC  
18  
I
I
I
I
I
9
21 I/O/Q  
I/O/Q  
I
I
I
11  
19  
18  
I/O/Q  
12  
14  
16  
Unique test circuitry and reprogrammable cells allow completeAC,  
DC, and functional testing during manufacture. As a result, Lattice  
Semiconductor delivers 100% field programmability and function-  
ality of all GAL products. In addition, 100 erase/write cycles and  
data retention in excess of 20 years are specified.  
12  
13 I/OE  
GND  
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
August 2006  
20v8_07  
1
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GAL20V8B-7LPN 替代型号

型号 品牌 替代类型 描述 数据表
GAL20V8B-10LPNI LATTICE

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GAL20V8B-10LPI LATTICE

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 High Performance E2CMOS PLD Generic Array Logic

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GAL20V8C-5LJN LATTICE

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GAL20V8C-7LJ LATTICE

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GAL20V8C-7LJN LATTICE

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