5秒后页面跳转
GAL20V8B-10LP PDF预览

GAL20V8B-10LP

更新时间: 2024-11-07 23:53:35
品牌 Logo 应用领域
莱迪思 - LATTICE 可编程逻辑器件光电二极管输入元件时钟
页数 文件大小 规格书
23页 309K
描述
Electrically-Erasable PLD

GAL20V8B-10LP 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:PLASTIC, DIP-24
针数:24Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.62Is Samacsys:N
其他特性:REGISTER PRELOAD; POWER-UP RESET架构:PAL-TYPE
最大时钟频率:58.8 MHzJESD-30 代码:R-PDIP-T24
JESD-609代码:e0长度:31.75 mm
专用输入次数:12I/O 线路数量:8
输入次数:20输出次数:8
产品条款数:64端子数量:24
最高工作温度:75 °C最低工作温度:
组织:12 DEDICATED INPUTS, 8 I/O输出函数:MACROCELL
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP24,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT APPLICABLE
电源:5 V可编程逻辑类型:EE PLD
传播延迟:10 ns认证状态:Not Qualified
座面最大高度:5.334 mm子类别:Programmable Logic Devices
最大供电电压:5.25 V最小供电电压:4.75 V
标称供电电压:5 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL EXTENDED
端子面层:Tin/Lead (Sn85Pb15)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT APPLICABLE宽度:7.62 mm
Base Number Matches:1

GAL20V8B-10LP 数据手册

 浏览型号GAL20V8B-10LP的Datasheet PDF文件第2页浏览型号GAL20V8B-10LP的Datasheet PDF文件第3页浏览型号GAL20V8B-10LP的Datasheet PDF文件第4页浏览型号GAL20V8B-10LP的Datasheet PDF文件第5页浏览型号GAL20V8B-10LP的Datasheet PDF文件第6页浏览型号GAL20V8B-10LP的Datasheet PDF文件第7页 
GAL20V8  
High Performance E2CMOS PLD  
Generic Array Logic™  
Features  
Functional Block Diagram  
HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
5 ns Maximum Propagation Delay  
Fmax = 166 MHz  
I/CLK  
I
IMUX  
I
CLK  
4 ns Maximum from Clock Input to Data Output  
UltraMOS® Advanced CMOS Technology  
I/O/Q  
8
8
OLMC  
50% to 75% REDUCTION IN POWER FROM BIPOLAR  
75mA Typ Icc on Low Power Device  
45mA Typ Icc on Quarter Power Device  
I
I
I
I
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
ACTIVE PULL-UPS ON ALL PINS  
E2 CELL TECHNOLOGY  
Reconfigurable Logic  
Reprogrammable Cells  
100% Tested/100% Yields  
High Speed Electrical Erasure (<100ms)  
20 Year Data Retention  
8
8
8
EIGHT OUTPUT LOGIC MACROCELLS  
Maximum Flexibility for Complex Logic Designs  
Programmable Output Polarity  
I
I
Also Emulates 24-pin PAL® Devices with Full Function/  
Fuse Map/Parametric Compatibility  
8
8
8
PRELOAD AND POWER-ON RESET OF ALL REGISTERS  
100% Functional Testability  
I
APPLICATIONS INCLUDE:  
DMA Control  
State Machine Control  
High Speed Graphics Processing  
Standard Logic Speed Upgrade  
OLMC  
IMUX  
I
I
OE  
I
I/OE  
ELECTRONIC SIGNATURE FOR IDENTIFICATION  
Description  
Pin Configuration  
The GAL20V8C, at 5ns maximum propagation delay time, com-  
bines a high performance CMOS process with Electrically Eras-  
able (E2) floating gate technology to provide the highest speed  
performance available in the PLD market. High speed erase times  
(<100ms) allow the devices to be reprogrammed quickly and ef-  
ficiently.  
DIP  
PLCC  
1
Vcc  
I
24  
I/CLK  
I
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I
I
I
I
I
4
2
28  
26  
GAL  
The generic architecture provides maximum design flexibility by  
allowing the Output Logic Macrocell (OLMC) to be configured by  
the user. An important subset of the many architecture configura-  
tions possible with the GAL20V8 are the PAL architectures listed  
in the table of the macrocell description section. GAL20V8 devices  
are capable of emulating any of these PAL architectures with full  
function/fuse map/parametric compatibility.  
5
7
I
I
I
25 I/O/Q  
20V8  
I/O/Q  
23  
I/O/Q  
NC  
6
GAL20V8  
Top View  
NC  
18  
I
I
I
I
I
9
21 I/O/Q  
I/O/Q  
I
I
I
11  
19  
18  
I/O/Q  
12  
14  
16  
Unique test circuitry and reprogrammable cells allow completeAC,  
DC, and functional testing during manufacture. As a result, Lattice  
Semiconductor delivers 100% field programmability and function-  
ality of all GAL products. In addition, 100 erase/write cycles and  
data retention in excess of 20 years are specified.  
12  
13 I/OE  
GND  
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
August 2000  
20v8_04  
1

GAL20V8B-10LP 替代型号

型号 品牌 替代类型 描述 数据表
GAL20V8B-10LPN LATTICE

完全替代

High Performance E2CMOS PLD Generic Array Log
PALCE20V8H-10PC/4 LATTICE

类似代替

EE CMOS 24-Pin Universal Programmable Array Logic

与GAL20V8B-10LP相关器件

型号 品牌 获取价格 描述 数据表
GAL20V8B-10LPI LATTICE

获取价格

High Performance E2CMOS PLD Generic Array Logic
GAL20V8B-10LPN LATTICE

获取价格

High Performance E2CMOS PLD Generic Array Log
GAL20V8B-10LPNI LATTICE

获取价格

High Performance E2CMOS PLD Generic Array Log
GAL20V8B-10LR/883 ETC

获取价格

Electrically-Erasable PLD
GAL20V8B-15LD/883 ETC

获取价格

Electrically-Erasable PLD
GAL20V8B-15LJ LATTICE

获取价格

High Performance E2CMOS PLD Generic Array Logic
GAL20V8B-15LJI LATTICE

获取价格

High Performance E2CMOS PLD Generic Array Logic
GAL20V8B-15LJN LATTICE

获取价格

High Performance E2CMOS PLD Generic Array Log
GAL20V8B-15LJNI LATTICE

获取价格

High Performance E2CMOS PLD Generic Array Log
GAL20V8B-15LP LATTICE

获取价格

High Performance E2CMOS PLD Generic Array Logic