Datasheet > GAL20V8Z

GAL20V8Z

更新时间： 2024-11-07 22:51:03

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
19页	307K
描述
Zero Power E2CMOS PLD

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中文翻译

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数据手册

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GAL20V8Z 数据手册

GAL20V8Z

GAL20V8ZD

Zero Power E²CMOS PLD

Features

Functional Block Diagram

• ZERO POWER E²CMOS TECHNOLOGY

— 100µA Standby Current

I/CLK

IMUX

— Input Transition Detection on GAL20V8Z

— Dedicated Power-down Pin on GAL20V8ZD

— Input and Output Latching During Power Down

• HIGH PERFORMANCE E²CMOS TECHNOLOGY

— 12 ns Maximum Propagation Delay

— Fmax = 83.3 MHz

— 8 ns Maximum from Clock Input to Data Output

— TTL Compatible 16 mA Output Drive

— UltraMOS^®Advanced CMOS Technology

• E²CELL TECHNOLOGY

— Reconfigurable Logic

— Reprogrammable Cells

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

CLK

I/O/Q

OLMC

I/O/Q

OLMC

I/DPP

• EIGHT OUTPUT LOGIC MACROCELLS

— Maximum Flexibility for Complex Logic Designs

— Programmable Output Polarity

— Architecturally Similar to Standard GAL20V8

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS

— 100% Functional Testability

• APPLICATIONS INCLUDE:

— Battery Powered Systems

— DMA Control

— State Machine Control

— High Speed Graphics Processing

OLMC

IMUX

I/OE

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

Description

Pin Configuration

DIP

The GAL20V8Z and GAL20V8ZD, at 100 µA standby current and

12ns propagation delay provides the highest speed and lowest

power combination PLD available in the market. The

GAL20V8Z/ZD is manufactured using Lattice Semiconductor's ad-

vanced zero power E²CMOS process, which combines CMOS with

Electrically Erasable (E²) floating gate technology.

I/CLK

2 4

Vcc

PLCC

I/DPP

I/O/Q

GAL

20V8Z

20V8ZD

2 8

I/O/Q

I/DPP

2 5 I/O/Q

The GAL20V8Z uses Input Transition Detection (ITD) to put the

device in standby mode and is capable of emulating the full func-

tionality of the standard GAL20V8. The GAL20V8ZD utilizes a

dedicated power-down pin (DPP) to put the device in standby mode.

It has 19 inputs available to the AND array.

I/O/Q

GAL20V8Z

GAL20V8ZD

Top View

2 3

2 1

I/O/Q

Unique test circuitry and reprogrammable cells allow completeAC,

DC, and functional testing during manufacture. As a result, Lattice

Semiconductor delivers 100% field programmability and function-

ality of all GAL products. In addition, 100 erase/write cycles and

data retention in excess of 20 years are specified.

1 1

1 9 I/O/Q

1 4

G N D

1 3

I/OE

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

December 1997

20v8zzd_03

12 3 4 5 6 7...19

中文翻译

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与GAL20V8Z相关器件

型号	品牌	获取价格	描述	数据表
GAL20V8Z-12QJ	LATTICE	获取价格	Zero Power E2CMOS PLD
GAL20V8Z-12QP	LATTICE	获取价格	Zero Power E2CMOS PLD
GAL20V8Z-15QJ	LATTICE	获取价格	Zero Power E2CMOS PLD
GAL20V8Z-15QP	LATTICE	获取价格	Zero Power E2CMOS PLD
GAL20V8ZD-12QJ	LATTICE	获取价格	Zero Power E2CMOS PLD
GAL20V8ZD-12QP	LATTICE	获取价格	Zero Power E2CMOS PLD
GAL20V8ZD-15QJ	LATTICE	获取价格	Zero Power E2CMOS PLD
GAL20V8ZD-15QP	LATTICE	获取价格	Zero Power E2CMOS PLD
GAL20VP8	LATTICE	获取价格	High-Speed E2CMOS PLD Generic Array Logic
GAL20VP8B-15LJ	LATTICE	获取价格	High-Speed E2CMOS PLD Generic Array Logic

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