Datasheet > GAL16V8D25LJ

GAL16V8D25LJ

更新时间： 2024-10-27 23:53:35

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
22页	308K
描述
IC-SM-CMOS EEPLD

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中文翻译

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数据手册

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GAL16V8D25LJ 数据手册

GAL16V8

High Performance E²CMOS PLD

Generic Array Logic™

Features

Functional Block Diagram

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

— 3.5 ns Maximum Propagation Delay

— Fmax = 250 MHz

I/CLK

CLK

— 3.0 ns Maximum from Clock Input to Data Output

I/O/Q

OLMC

— UltraMOS^®Advanced CMOS Technology

• 50% to 75% REDUCTION IN POWER FROM BIPOLAR

— 75mA Typ Icc on Low Power Device

— 45mA Typ Icc on Quarter Power Device

OLMC

• ACTIVE PULL-UPS ON ALL PINS

• E²CELL TECHNOLOGY

— Reconfigurable Logic

— Reprogrammable Cells

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

• EIGHT OUTPUT LOGIC MACROCELLS

— Maximum Flexibility for Complex Logic Designs

— Programmable Output Polarity

— Also Emulates 20-pin PAL^®Devices with Full

Function/Fuse Map/Parametric Compatibility

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS

— 100% Functional Testability

• APPLICATIONS INCLUDE:

— DMA Control

— State Machine Control

— High Speed Graphics Processing

— Standard Logic Speed Upgrade

I/O/Q

I/OE

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

Description

Pin Configuration

The GAL16V8, at 3.5 ns maximum propagation delay time, com-

bines a high performance CMOS process with Electrically Eras-

able (E²) floating gate technology to provide the highest speed

performance available in the PLD market. High speed erase times

(<100ms) allow the devices to be reprogrammed quickly and ef-

ficiently.

DIP

Vcc

I/CLK

PLCC

I/O/Q

I/OE

I/CLK Vcc I/O/Q

The generic architecture provides maximum design flexibility by

allowing the Output Logic Macrocell (OLMC) to be configured by

the user. An important subset of the many architecture configura-

tions possible with the GAL16V8 are the PAL architectures listed

in the table of the macrocell description section. GAL16V8 devices

are capable of emulating any of these PAL architectures with full

function/fuse map/parametric compatibility.

GAL

I/O/Q

16V8

I/O/Q

GAL16V8

Top View

I/O/Q

Unique test circuitry and reprogrammable cells allow completeAC,

DC, and functional testing during manufacture. As a result, Lattice

Semiconductor delivers 100% field programmability and function-

ality of all GAL products. In addition, 100 erase/write cycles and

data retention in excess of 20 years are specified.

GND I/OE I/O/Q I/O/Q

GND

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

August 2000

16v8_07

12 3 4 5 6 7...22

中文翻译

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与GAL16V8D25LJ相关器件

型号	品牌	获取价格	描述	数据表
GAL16V8D-25LJ	LATTICE	获取价格	High Performance E2CMOS PLD Generic Array Logic
GAL16V8D-25LJI	LATTICE	获取价格	High Performance E2CMOS PLD Generic Array Logic
GAL16V8D-25LJN	LATTICE	获取价格	High Performance E2CMOS PLD Generic Array Log
GAL16V8D-25LJNI	LATTICE	获取价格	High Performance E2CMOS PLD Generic Array Log
GAL16V8D25LP	ETC	获取价格	IC-CMOS PLD
GAL16V8D-25LP	LATTICE	获取价格	High Performance E2CMOS PLD Generic Array Logic
GAL16V8D-25LPI	LATTICE	获取价格	High Performance E2CMOS PLD Generic Array Logic
GAL16V8D-25LPN	LATTICE	获取价格	High Performance E2CMOS PLD Generic Array Log
GAL16V8D-25LPNI	LATTICE	获取价格	High Performance E2CMOS PLD Generic Array Log
GAL16V8D-25LS	LATTICE	获取价格	High Performance E2CMOS PLD Generic Array Logic

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