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GAL16V8D-30LD/833 PDF预览

GAL16V8D-30LD/833

更新时间： 2024-11-07 22:07:47
品牌 Logo 应用领域
莱迪思 - LATTICE /
页数 文件大小 规格书
8页 108K
描述
High Performance E2CMOS PLD Generic Array Logic

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中文翻译

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GAL16V8D-30LD/833 数据手册

 浏览型号GAL16V8D-30LD/833的Datasheet PDF文件第2页浏览型号GAL16V8D-30LD/833的Datasheet PDF文件第3页浏览型号GAL16V8D-30LD/833的Datasheet PDF文件第4页浏览型号GAL16V8D-30LD/833的Datasheet PDF文件第5页浏览型号GAL16V8D-30LD/833的Datasheet PDF文件第6页浏览型号GAL16V8D-30LD/833的Datasheet PDF文件第7页 
GAL16V8/883  
High Performance E2CMOS PLD  
Generic Array Logic™  
Features  
Functional Block Diagram  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
— 7.5 ns Maximum Propagation Delay  
— Fmax = 100 MHz  
I/CLK  
CLK  
— 6 ns Maximum from Clock Input to Data Output  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
8
8
OLMC  
— TTL Compatible 12 mA Outputs  
I
I
I
I
I
I
I
I
— UltraMOS® Advanced CMOS Technology  
• 50% REDUCTION IN POWER FROM BIPOLAR  
— 75mA Typ Icc  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
• ACTIVE PULL-UPS ON ALL PINS (GAL16V8D-7 and  
GAL16V8D-10)  
• E2 CELL TECHNOLOGY  
— Reconfigurable Logic  
— Reprogrammable Cells  
— 100% Tested/100% Yields  
— High Speed Electrical Erasure (<100ms)  
— 20 Year Data Retention  
8
8
8
8
8
8
• EIGHT OUTPUT LOGIC MACROCELLS  
— Maximum Flexibility for Complex Logic Designs  
— Programmable Output Polarity  
— Also Emulates 20-pin PAL® Devices with Full Function/  
Fuse Map/Parametric Compatibility  
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS  
— 100% Functional Testability  
• APPLICATIONS INCLUDE:  
— DMA Control  
— State Machine Control  
— High Speed Graphics Processing  
— Standard Logic Speed Upgrade  
I/O/Q  
I/OE  
OE  
• ELECTRONIC SIGNATURE FOR IDENTIFICATION  
Description  
Pin Configuration  
The GAL16V8/883 is a high performance E2CMOS program-  
mablelogicdeviceprocessedinfullcomplianceto MIL-STD-883.  
This military grade device combines a high performance CMOS  
process with Electrically Erasable (E2) floating gate technology to  
provide the highest speed/power performance available in the  
883 qualified PLD market. The GAL16V8D/883, at 7.5ns maxi-  
mum propagation delay time, is the world's fastest military quali-  
fied CMOS PLD.  
CERDIP  
LCC  
1
20  
Vcc  
I/CLK  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/OE  
I
I
I
I/CLK Vcc I/O/Q  
20 19  
I
I
3
2
GAL  
4
6
18  
I/O/Q  
I
The generic GAL architecture provides maximum design flexibil-  
ity by allowing the Output Logic Macrocell (OLMC) to be config-  
ured by the user. The GAL16V8/883 is capable of emulating all  
standard 20-pin PAL® devices with full function/fuse map/para-  
metric compatibility.  
16V8  
5
I/O/Q  
I/O/Q  
I
I
I
GAL16V8  
Top View  
16  
I
15  
I/O/Q  
I/O/Q  
I
I
I
8
14  
I
Unique test circuitry and reprogrammable cells allow complete  
AC, DC, and functional testing during manufacture. Therefore,  
Lattice Semiconductor delivers 100% field programmability and  
functionality of all GAL products. In addition, 100 erase/write  
cycles and data retention in excess of 20 years are specified.  
9
11  
13  
I
GND I/OE I/O/Q I/O/Q  
I
10  
11  
GND  
Copyright © 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
February 1999  
16v8mil_03  
1
12345678

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GAL16V8D-7LD/833 LATTICE

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