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FQPF20N06L PDF预览

FQPF20N06L

更新时间: 2024-11-15 22:51:03
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
8页 663K
描述
60V LOGIC N-Channel MOSFET

FQPF20N06L 数据手册

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May 2001  
TM  
QFET  
FQPF20N06L  
60V LOGIC N-Channel MOSFET  
General Description  
Features  
These N-Channel enhancement mode power field effect  
transistors are produced using Fairchild’s proprietary,  
planar stripe, DMOS technology.  
This advanced technology has been especially tailored to  
minimize on-state resistance, provide superior switching  
performance, and withstand high energy pulse in the  
avalanche and commutation mode. These devices are well  
suited for low voltage applications such as automotive, DC/  
DC converters, and high efficiency switching for power  
management in portable and battery operated products.  
15.7A, 60V, R  
= 0.055@V = 10 V  
DS(on) GS  
Low gate charge ( typical 9.5 nC)  
Low Crss ( typical 35 pF)  
Fast switching  
100% avalanche tested  
Improved dv/dt capability  
175°C maximum junction temperature rating  
D
!
"
! "  
"
G !  
"
G D  
S
TO-220F  
FQPF Series  
!
S
Absolute Maximum Ratings  
T = 25°C unless otherwise noted  
C
Symbol  
Parameter  
FQPF20N06L  
Units  
V
V
I
Drain-Source Voltage  
60  
15.7  
11.1  
62.8  
± 20  
170  
DSS  
- Continuous (T = 25°C)  
Drain Current  
A
D
C
- Continuous (T = 100°C)  
A
C
I
(Note 1)  
Drain Current  
- Pulsed  
A
DM  
V
E
I
Gate-Source Voltage  
V
GSS  
(Note 2)  
(Note 1)  
(Note 1)  
(Note 3)  
Single Pulsed Avalanche Energy  
Avalanche Current  
mJ  
A
AS  
15.7  
3.0  
AR  
E
Repetitive Avalanche Energy  
Peak Diode Recovery dv/dt  
mJ  
V/ns  
W
AR  
dv/dt  
7.0  
P
Power Dissipation (T = 25°C)  
30  
D
C
- Derate above 25°C  
Operating and Storage Temperature Range  
0.2  
W/°C  
°C  
T , T  
-55 to +175  
J
STG  
Maximum lead temperature for soldering purposes,  
T
300  
°C  
L
1/8" from case for 5 seconds  
Thermal Characteristics  
Symbol  
Parameter  
Typ  
Max  
5.00  
62.5  
Units  
°C/W  
°C/W  
R
R
Thermal Resistance, Junction-to-Case  
Thermal Resistance, Junction-to-Ambient  
--  
--  
θJC  
θJA  
©2001 Fairchild Semiconductor Corporation  
Rev. A1. May 2001  

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