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FDMA410NZT-F130 PDF预览

FDMA410NZT-F130

更新时间: 2023-09-03 20:31:56
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
8页 419K
描述
超薄 N 沟道,1.5 V,PowerTrench® MOSFET,20V,9.5A,23mΩ

FDMA410NZT-F130 数据手册

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FDMA410NZT  
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)  
J
Symbol  
Parameter  
Test Conditions  
Min  
Typ  
Max  
Unit  
DYNAMIC CHARACTERISTICS  
C
Input Capacitance  
V
= 10 V, V = 0 V, f = 1 MHz  
935  
122  
84  
1310  
170  
118  
3.0  
pF  
pF  
pF  
W
iss  
DS  
GS  
C
Output Capacitance  
Reverse Transfer Capacitance  
Gate Resistance  
oss  
C
rss  
R
f = 1 MHz  
0.1  
1.4  
g
SWITCHING CHARACTERISTICS  
t
Turnon Delay Time  
Rise Time  
V
= 10 V, I = 9.5 A, VGS = 4.5 V,  
GEN  
8.5  
3.0  
27  
17  
10  
44  
10  
14  
ns  
d(on)  
DD  
D
R
= 6 W  
t
r
t
Turnoff Delay Time  
Fall Time  
d(off)  
t
f
3.3  
10  
Q
Total Gate Charge  
Gate to Source Charge  
Gate to Drain “Miller” Charge  
V
GS  
= 4.5 V, V = 10 V, I = 9.5 A  
nC  
g
DD  
D
Q
1.2  
2.0  
gs  
gd  
Q
DRAINSOURCE DIODE CHARACTERISTICS  
Maximum Continuous DrainSource Diode Forward Current  
I
S
2.0  
1.2  
30  
A
V
V
Source to Drain Diode Forward Voltage  
Reverse Recovery Time  
V
= 0 V, I = 2 A (Note 2)  
0.7  
16  
SD  
GS  
S
t
I = 9.5 A, di/dt = 100 A/ms  
F
ns  
nC  
rr  
Q
Reverse Recovery Charge  
4.5  
10  
rr  
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product  
performance may not be indicated by the Electrical Characteristics if operated under different conditions.  
NOTES:  
2
1. R  
is determined with the device mounted on a 1 in pad 2 oz copper pad on a 1.5 × 1.5 in. board of FR4 material. RθJA is determined by  
q
JA  
the user’s board design.  
a) 52°C/W when mounted on  
b) 145°C/W when mounted on  
2
a 1 in pad of 2 oz copper.  
a minimum pad of 2 oz copper.  
2. Pulse Test: Pulse Width < 300 ms, Duty cycle < 2.0%.  
3. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.  
4. Pulsed Id please refer to Figure 11 SOA curve for more details.  
www.onsemi.com  
3
 

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