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EPM7064AETI44-7 PDF预览

EPM7064AETI44-7

更新时间: 2024-01-24 02:29:21
品牌 Logo 应用领域
阿尔特拉 - ALTERA 时钟输入元件可编程逻辑
页数 文件大小 规格书
64页 437K
描述
EE PLD, 7.5ns, 64-Cell, CMOS, PQFP44, TQFP-44

EPM7064AETI44-7 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:QFP
包装说明:LQFP, TQFP44,.47SQ,32针数:44
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:3.85
Samacsys Description:Programmable Logic Device架构:PLA-TYPE
最大时钟频率:135.1 MHz系统内可编程:YES
JESD-30 代码:S-PQFP-G44JESD-609代码:e3
JTAG BST:YES长度:10 mm
湿度敏感等级:3专用输入次数:
I/O 线路数量:36输入次数:36
宏单元数:64输出次数:36
产品条款数:2048端子数量:44
最高工作温度:85 °C最低工作温度:-40 °C
组织:0 DEDICATED INPUTS, 36 I/O输出函数:MACROCELL
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:TQFP44,.47SQ,32封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):260
电源:2.5/3.3,3.3 V可编程逻辑类型:EE PLD
传播延迟:7.5 ns认证状态:Not Qualified
座面最大高度:1.27 mm子类别:Programmable Logic Devices
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:10 mm

EPM7064AETI44-7 数据手册

 浏览型号EPM7064AETI44-7的Datasheet PDF文件第2页浏览型号EPM7064AETI44-7的Datasheet PDF文件第3页浏览型号EPM7064AETI44-7的Datasheet PDF文件第4页浏览型号EPM7064AETI44-7的Datasheet PDF文件第5页浏览型号EPM7064AETI44-7的Datasheet PDF文件第6页浏览型号EPM7064AETI44-7的Datasheet PDF文件第7页 
MAX 7000A  
Programmable Logic  
Device  
Includes  
MAX 7000AE  
®
September 2003, ver. 4.5  
Data Sheet  
High-performance 3.3-V EEPROM-based programmable logic  
devices (PLDs) built on second-generation Multiple Array MatriX  
(MAX®) architecture (see Table 1)  
3.3-V in-system programmability (ISP) through the built-in  
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with  
advanced pin-locking capability  
Features...  
MAX 7000AE device in-system programmability (ISP) circuitry  
compliant with IEEE Std. 1532  
EPM7128A and EPM7256A device ISP circuitry compatible with  
IEEE Std. 1532  
Built-in boundary-scan test (BST) circuitry compliant with  
IEEE Std. 1149.1  
Supports JEDEC Jam Standard Test and Programming Language  
(STAPL) JESD-71  
Enhanced ISP features  
Enhanced ISP algorithm for faster programming (excluding  
EPM7128A and EPM7256A devices)  
ISP_Done bit to ensure complete programming (excluding  
EPM7128A and EPM7256A devices)  
Pull-up resistor on I/O pins during in-system programming  
Pin-compatible with the popular 5.0-V MAX 7000S devices  
High-density PLDs ranging from 600 to 10,000 usable gates  
Extended temperature range  
For information on in-system programmable 5.0-V MAX 7000 or 2.5-V  
MAX 7000B devices, see the MAX 7000 Programmable Logic Device Family  
Data Sheet or the MAX 7000B Programmable Logic Device Family Data Sheet.  
f
Altera Corporation  
1
DS-M7000A-4.5  

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