Datasheet > EPM7064AEUC49-7

EPM7064AEUC49-7

更新时间： 2024-02-08 15:00:28

品牌	Logo	应用领域
阿尔特拉 - ALTERA		/
页数	文件大小	规格书
60页	876K
描述
EE PLD, 7.5ns, CMOS, PBGA49, ULTRA FINE LINE, BGA-49

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EPM7064AEUC49-7 数据手册

MAX 7000A

Programmable Logic

Device

Includes

MAX 7000AE

September 2002, ver. 4.2

Data Sheet

■

High-performance 3.3-V EEPROM-based programmable logic

devices (PLDs) built on second-generation Multiple Array MatriX

(MAX^®) architecture (see Table 1)

3.3-V in-system programmability (ISP) through the built-in

IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with

advanced pin-locking capability

Features...

–

MAX 7000AE device in-system programmability (ISP) circuitry

compliant with IEEE Std. 1532

–

EPM7128A and EPM7256A device ISP circuitry compatible with

IEEE Std. 1532

■

Built-in boundary-scan test (BST) circuitry compliant with

IEEE Std. 1149.1

Supports JEDEC Jam Standard Test and Programming Language

(STAPL) JESD-71

Enhanced ISP features

–

Enhanced ISP algorithm for faster programming (excluding

EPM7128A and EPM7256A devices)

ISP_Done bit to ensure complete programming (excluding

EPM7128A and EPM7256A devices)

Pull-up resistor on I/O pins during in-system programming

■

Pin-compatible with the popular 5.0-V MAX 7000S devices

High-density PLDs ranging from 600 to 10,000 usable gates

For information on in-system programmable 5.0-V MAX 7000 or 2.5-V

MAX 7000B devices, see the MAX 7000 Programmable Logic Device Family

Data Sheet or the MAX 7000B Programmable Logic Device Family Data Sheet.

Table 1. MAX 7000A Device Features

Feature

EPM7032AE

EPM7064AE

EPM7128AE

EPM7256AE

EPM7512AE

Usable gates

Macrocells

600

1,250

2,500

128

5,000

256

10,000

512

Logic array blocks

Maximum user I/O

pins

100

164

212

_PD(ns)

t_SU(ns)

_FSU(ns)

4.5

2.9

4.5

2.8

5.0

3.3

5.5

3.9

7.5

5.6

2.5

3.0

t_CO1(ns)

3.0

3.1

3.4

3.5

4.7

f_CNT(MHz)

227.3

222.2

192.3

172.4

116.3

Altera Corporation

DS-M7000A-4.2

12 3 4 5 6 7...60

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