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EPM7064BFC100-5N

更新时间： 2024-11-03 07:38:55

品牌	Logo	应用领域
英特尔 - INTEL		时钟输入元件可编程逻辑器件
页数	文件大小	规格书
76页	1516K
描述
EE PLD, 3.5ns, 64-Cell, CMOS, PBGA100, FBGA-100

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EPM7064BFC100-5N 数据手册

MAX 7000B

Programmable Logic

Device

September 2005, ver. 3.5

Data Sheet

■

High-performance 2.5-V CMOS EEPROM-based programmable logic

devices (PLDs) built on second-generation Multiple Array MatriX

(MAX^®) architecture (see Table 1)

Features...

–

Pin-compatible with the popular 5.0-V MAX 7000S and 3.3-V

MAX 7000A device families

–

High-density PLDs ranging from 600 to 10,000 usable gates

3.5-ns pin-to-pin logic delays with counter frequencies in excess

of 303.0 MHz

■

Advanced 2.5-V in-system programmability (ISP)

–

Programs through the built-in IEEE Std. 1149.1 Joint Test Action

Group (JTAG) interface with advanced pin-locking capability

Enhanced ISP algorithm for faster programming

ISP_Done bit to ensure complete programming

Pull-up resistor on I/O pins during in-system programming

ISP circuitry compliant with IEEE Std. 1532

–

For information on in-system programmable 5.0-V MAX 7000S or 3.3-V

MAX 7000A devices, see the MAX 7000 Programmable Logic Device Family

Data Sheet or the MAX 7000A Programmable Logic Device Family Data Sheet.

Table 1. MAX 7000B Device Features

Feature

EPM7032B

EPM7064B

EPM7128B

EPM7256B

EPM7512B

Usable gates

Macrocells

600

1,250

2,500

128

5,000

256

10,000

512

Logic array blocks

Maximum user I/O

pins

100

164

212

_PD(ns)

_SU(ns)

3.5

2.1

3.5

2.1

4.0

2.5

5.0

3.3

5.5

3.6

t_FSU(ns)

_CO1(ns)

1.0

2.4

2.8

3.3

3.7

f_CNT(MHz)

303.0

243.9

188.7

163.9

Altera Corporation

DS-MAX7000B-3.5

12 3 4 5 6 7...76

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