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EPF6016ATC144-2N PDF预览

EPF6016ATC144-2N

更新时间: 2024-02-12 20:30:48
品牌 Logo 应用领域
阿尔特拉 - ALTERA 可编程逻辑器件输入元件时钟
页数 文件大小 规格书
52页 394K
描述
Programmable Logic Device Family

EPF6016ATC144-2N 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:QFP
包装说明:LFQFP, QFP144,.63SQ,20针数:144
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:7.72
其他特性:CAN ALSO BE USED 16000 LOGIC GATES最大时钟频率:153 MHz
JESD-30 代码:S-PQFP-G144JESD-609代码:e3
长度:20 mm湿度敏感等级:3
专用输入次数:4I/O 线路数量:117
输入次数:117逻辑单元数量:1320
输出次数:117端子数量:144
最高工作温度:85 °C最低工作温度:
组织:4 DEDICATED INPUTS, 117 I/O输出函数:MACROCELL
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP144,.63SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):260
电源:2.5/3.3,3.3 V可编程逻辑类型:LOADABLE PLD
认证状态:Not Qualified座面最大高度:1.6 mm
子类别:Field Programmable Gate Arrays最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子面层:MATTE TIN (472) OVER COPPER
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:20 mmBase Number Matches:1

EPF6016ATC144-2N 数据手册

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FLEX 6000 Programmable Logic Device Family Data Sheet  
Powerful I/O pins  
...and More  
Features  
Individual tri-state output enable control for each pin  
Programmable output slew-rate control to reduce switching  
noise  
Fast path from register to I/O pin for fast clock-to-output time  
Flexible interconnect  
FastTrack® Interconnect continuous routing structure for fast,  
predictable interconnect delays  
Dedicated carry chain that implements arithmetic functions such  
as fast adders, counters, and comparators (automatically used by  
software tools and megafunctions)  
Dedicated cascade chain that implements high-speed, high-fan-  
in logic functions (automatically used by software tools and  
megafunctions)  
Tri-state emulation that implements internal tri-state networks  
Four low-skew global paths for clock, clear, preset, or logic  
signals  
Software design support and automatic place-and-route provided by  
Altera’s development system for Windows-based PCs, Sun  
SPARCstations, and HP 9000 Series 700/800  
Flexible package options  
Available in a variety of packages with 100 to 256 pins, including  
the innovative FineLine BGATM packages (see Table 2)  
SameFrameTM pin-compatibility (with other FLEX® 6000 devices)  
across device densities and pin counts  
Thin quad flat pack (TQFP), plastic quad flat pack (PQFP), and  
ball-grid array (BGA) packages (see Table 2)  
Footprint- and pin-compatibility with other FLEX 6000 devices  
in the same package  
Additional design entry and simulation support provided by  
EDIF 2 0 0 and 3 0 0 netlist files, the library of parameterized modules  
(LPM), Verilog HDL, VHDL, DesignWare components, and other  
interfaces to popular EDA tools from manufacturers such as  
Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys,  
Synplicity, VeriBest, and Viewlogic  
Table 2. FLEX 6000 Package Options & I/O Pin Count  
Device  
100-Pin  
TQFP  
100-Pin  
FineLine BGA  
144-Pin  
TQFP  
208-Pin  
PQFP  
240-Pin  
PQFP  
256-Pin  
BGA  
256-pin  
FineLine BGA  
EPF6010A  
EPF6016  
71  
102  
117  
117  
117  
171  
171  
171  
199  
199  
204  
218  
EPF6016A  
EPF6024A  
81  
81  
171  
219  
2
Altera Corporation  

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