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EPF6016TC100-2 PDF预览

EPF6016TC100-2

更新时间: 2024-01-04 04:55:58
品牌 Logo 应用领域
阿尔特拉 - ALTERA 可编程逻辑器件
页数 文件大小 规格书
52页 394K
描述
Programmable Logic Device Family

EPF6016TC100-2 技术参数

是否Rohs认证: 不符合生命周期:Contact Manufacturer
包装说明:QFP, QFP100,.63SQ,20Reach Compliance Code:compliant
风险等级:5.57JESD-30 代码:S-PQFP-G100
输入次数:81逻辑单元数量:1320
输出次数:81端子数量:100
封装主体材料:PLASTIC封装代码:QFP
封装等效代码:QFP100,.63SQ,20封装形状:SQUARE
封装形式:FLATPACK电源:5 V
可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY认证状态:Not Qualified
子类别:Field Programmable Gate Arrays标称供电电压:5 V
表面贴装:YES技术:CMOS
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUADBase Number Matches:1

EPF6016TC100-2 数据手册

 浏览型号EPF6016TC100-2的Datasheet PDF文件第2页浏览型号EPF6016TC100-2的Datasheet PDF文件第3页浏览型号EPF6016TC100-2的Datasheet PDF文件第4页浏览型号EPF6016TC100-2的Datasheet PDF文件第5页浏览型号EPF6016TC100-2的Datasheet PDF文件第6页浏览型号EPF6016TC100-2的Datasheet PDF文件第7页 
FLEX 6000  
Programmable Logic  
Device Family  
®
March 2001, ver. 4.1  
Data Sheet  
Provides an ideal low-cost, programmable alternative to high-  
volume gate array applications and allows fast design changes  
during prototyping or design testing  
Features...  
Product features  
Register-rich, look-up table- (LUT-) based architecture  
OptiFLEX® architecture that increases device area efficiency  
Typical gates ranging from 5,000 to 24,000 gates (see Table 1)  
Built-in low-skew clock distribution tree  
100% functional testing of all devices; test vectors or scan chains  
are not required  
System-level features  
In-circuit reconfigurability (ICR) via external configuration  
device or intelligent controller  
5.0-V devices are fully compliant with peripheral component  
interconnect Special Interest Group (PCI SIG) PCI Local Bus  
Specification, Revision 2.2  
Built-in Joint Test Action Group (JTAG) boundary-scan test  
(BST) circuitry compliant with IEEE Std. 1149.1-1990, available  
without consuming additional device logic  
MultiVoltTM I/O interface operation, allowing a device to bridge  
between systems operating at different voltages  
Low power consumption (typical specification less than 0.5 mA  
in standby mode)  
3.3-V devices support hot-socketing  
Table 1. FLEX 6000 Device Features  
Feature  
EPF6010A  
EPF6016  
EPF6016A  
EPF6024A  
Typical gates (1)  
10,000  
880  
16,000  
1,320  
204  
16,000  
1,320  
171  
24,000  
1,960  
218  
Logic elements (LEs)  
Maximum I/O pins  
Supply voltage (VCCINT  
102  
)
3.3 V  
5.0 V  
3.3 V  
3.3 V  
Note:  
(1) The embedded IEEE Std. 1149.1 JTAG circuitry adds up to 14,000 gates in addition to the listed typical gates.  
Altera Corporation  
1
A-DS-F6000-04.1  

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