EPF6016ATC100-2

更新时间： 2024-02-13 15:00:24

品牌	Logo	应用领域
阿尔特拉 - ALTERA		可编程逻辑器件
页数	文件大小	规格书
52页	394K
描述
Programmable Logic Device Family

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EPF6016ATC100-2 数据手册

FLEX 6000 Programmable Logic Device Family Data Sheet

The FLEX 6000 OptiFLEX architecture consists of logic elements (LEs).

Each LE includes a 4-input look-up table (LUT), which can implement any

4-input function, a register, and dedicated paths for carry and cascade

chain functions. Because each LE contains a register, a design can be easily

pipelined without consuming more LEs. The specified gate count for

FLEX 6000 devices includes all LUTs and registers.

Functional

Description

LEs are combined into groups called logic array blocks (LABs); each LAB

contains 10 LEs. The Altera software automatically places related LEs into

the same LAB, minimizing the number of required interconnects. Each

LAB can implement a medium-sized block of logic, such as a counter or

multiplexer.

Signal interconnections within FLEX 6000 devices—and to and from

device pins—are provided via the routing structure of the FastTrack

Interconnect. The routing structure is a series of fast, continuous row and

column channels that run the entire length and width of the device. Any

LE or pin can feed or be fed by any other LE or pin via the FastTrack

Interconnect. See “FastTrack Interconnect” on page 17 of this data sheet

for more information.

Each I/O pin is fed by an I/O element (IOE) located at the end of each row

and column of the FastTrack Interconnect. Each IOE contains a

bidirectional I/O buffer. Each IOE is placed next to an LAB, where it can

be driven by the local interconnect of that LAB. This feature allows fast

clock-to-output times of less than 8 ns when a pin is driven by any of the

10 LEs in the adjacent LAB. Also, any LE can drive any pin via the row and

column interconnect. I/O pins can drive the LE registers via the row and

column interconnect, providing setup times as low as 2 ns and hold times

of 0 ns. IOEs provide a variety of features, such as JTAG BST support,

slew-rate control, and tri-state buffers.

Figure 1 shows a block diagram of the FLEX 6000 OptiFLEX architecture.

Each group of ten LEs is combined into an LAB, and the LABs are

arranged into rows and columns. The LABs are interconnected by the

FastTrack Interconnect. IOEs are located at the end of each FastTrack

Interconnect row and column.

Altera Corporation

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型号	品牌	描述	获取价格	数据表
EPF6016ATC100-2N	ALTERA	Loadable PLD, PQFP100, TQFP-100	获取价格
EPF6016ATC100-3	ALTERA	Loadable PLD, CMOS, PQFP100, TQFP-100	获取价格
EPF6016ATC100-3N	ALTERA	Loadable PLD, PQFP100, TQFP-100	获取价格
EPF6016ATC144-1	ALTERA	Loadable PLD, CMOS, PQFP144, TQFP-144	获取价格
EPF6016ATC144-2N	ALTERA	Programmable Logic Device Family	获取价格
EPF6016ATC144-3	ALTERA	Loadable PLD, CMOS, PQFP144, TQFP-144	获取价格