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EPF6010ATC100-1N PDF预览

EPF6010ATC100-1N

更新时间: 2024-11-06 20:58:51
品牌 Logo 应用领域
阿尔特拉 - ALTERA 时钟输入元件可编程逻辑
页数 文件大小 规格书
52页 374K
描述
Loadable PLD, PQFP100, TQFP-100

EPF6010ATC100-1N 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:QFP
包装说明:LFQFP,针数:100
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.18
其他特性:CAN ALSO BE USED 10000 LOGIC GATES最大时钟频率:172 MHz
JESD-30 代码:S-PQFP-G100JESD-609代码:e3
长度:14 mm湿度敏感等级:3
专用输入次数:4I/O 线路数量:71
端子数量:100最高工作温度:85 °C
最低工作温度:组织:4 DEDICATED INPUTS, 71 I/O
输出函数:MACROCELL封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):260
可编程逻辑类型:LOADABLE PLD认证状态:Not Qualified
座面最大高度:1.27 mm最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES温度等级:OTHER
端子面层:MATTE TIN (472) OVER COPPER端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:14 mm
Base Number Matches:1

EPF6010ATC100-1N 数据手册

 浏览型号EPF6010ATC100-1N的Datasheet PDF文件第2页浏览型号EPF6010ATC100-1N的Datasheet PDF文件第3页浏览型号EPF6010ATC100-1N的Datasheet PDF文件第4页浏览型号EPF6010ATC100-1N的Datasheet PDF文件第5页浏览型号EPF6010ATC100-1N的Datasheet PDF文件第6页浏览型号EPF6010ATC100-1N的Datasheet PDF文件第7页 
FLEX 6000  
Programmable Logic  
Device Family  
®
March 2001, ver. 4.1  
Data Sheet  
Provides an ideal low-cost, programmable alternative to high-  
volume gate array applications and allows fast design changes  
during prototyping or design testing  
Features...  
Product features  
Register-rich, look-up table- (LUT-) based architecture  
OptiFLEX® architecture that increases device area efficiency  
Typical gates ranging from 5,000 to 24,000 gates (see Table 1)  
Built-in low-skew clock distribution tree  
100% functional testing of all devices; test vectors or scan chains  
are not required  
System-level features  
In-circuit reconfigurability (ICR) via external configuration  
device or intelligent controller  
5.0-V devices are fully compliant with peripheral component  
interconnect Special Interest Group (PCI SIG) PCI Local Bus  
Specification, Revision 2.2  
Built-in Joint Test Action Group (JTAG) boundary-scan test  
(BST) circuitry compliant with IEEE Std. 1149.1-1990, available  
without consuming additional device logic  
MultiVoltTM I/O interface operation, allowing a device to bridge  
between systems operating at different voltages  
Low power consumption (typical specification less than 0.5 mA  
in standby mode)  
3.3-V devices support hot-socketing  
Table 1. FLEX 6000 Device Features  
Feature  
EPF6010A  
EPF6016  
EPF6016A  
EPF6024A  
Typical gates (1)  
10,000  
880  
16,000  
1,320  
204  
16,000  
1,320  
171  
24,000  
1,960  
218  
Logic elements (LEs)  
Maximum I/O pins  
Supply voltage (VCCINT  
102  
)
3.3 V  
5.0 V  
3.3 V  
3.3 V  
Note:  
(1) The embedded IEEE Std. 1149.1 JTAG circuitry adds up to 14,000 gates in addition to the listed typical gates.  
Altera Corporation  
1
A-DS-F6000-04.1  
 
 

EPF6010ATC100-1N 替代型号

型号 品牌 替代类型 描述 数据表
EPF6010ATC100-3 ALTERA

完全替代

Loadable PLD, CMOS, PQFP100, TQFP-100

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