Datasheet > EP1K50TI144-2P

EP1K50TI144-2P

更新时间： 2024-11-01 23:50:43

品牌	Logo	应用领域
其他 - ETC		现场可编程门阵列栅
页数	文件大小	规格书
86页	1180K
描述
Field Programmable Gate Array (FPGA)

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EP1K50TI144-2P 数据手册

ACEX 1K

Programmable Logic Device Family

June 2001, ver. 3.1

Data Sheet

Programmable logic devices (PLDs), providing low cost

system-on-a-programmable-chip (SOPC) integration in a single

device

Features...

–

Enhanced embedded array for implementing megafunctions

such as efficient memory and specialized logic functions

Dual-port capability with up to 16-bit width per embedded array

block (EAB)

Logic array for general logic functions

High density

–

10,000 to 100,000 typical gates (see Table 1)

Up to 49,152 RAM bits (4,096 bits per EAB, all of which can be

used without reducing logic capacity)

Cost-efficient programmable architecture for high-volume

applications

–

Cost-optimized process

Low cost solution for high-performance communications

applications

System-level features

–

MultiVolt^TMI/ O pins can drive or be driven by 2.5-V, 3.3-V, or

5.0-V devices

–

Low power consumption

Bidirectional I/ O performance (setup time [t ] and clock-to-

output delay [t ]) up to 250 MHz

–

Fully compliant with the peripheral component interconnect

Special Interest Group (PCI SIG) PCI Local Bus Specification,

Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz

Table 1. ACEX 1K Device Features

Feature

EP1K10

EP1K30

EP1K50

EP1K100

Typical gates

10,000

56,000

576

30,000

119,000

1,728

50,000

199,000

2,880

100,000

257,000

4,992

Maximum system gates

Logic elements (LEs)

EABs

Total RAM bits

12,288

136

24,576

171

40,960

249

49,152

333

Maximum user I/O pins

Altera Corporation

A-DS-ACEX-3.1

12 3 4 5 6 7...86

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