Datasheet > EP1M120FI484-6

EP1M120FI484-6

更新时间： 2023-02-26 15:55:12

品牌	Logo	应用领域
阿尔特拉 - ALTERA		/
页数	文件大小	规格书
84页	936K
描述
Loadable PLD, CMOS, PBGA484, 23 X 23 MM, 1 MM PITCH, FINE LINE, BGA-484

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EP1M120FI484-6 数据手册

Mercury

Programmable Logic

Device Family

February 2001, ver. 1.1

Data Sheet

ꢀ

High-performance programmable logic device (PLD) family (see

Table 1)

Features…

–

Integrated high-speed transceivers with support for clock data

recovery (CDR) at up to 1.25 gigabits per second (Gbps)

Look-up table (LUT)-based architecture optimized for high

speed

–

Advanced interconnect structure for fast routing of critical paths

Enhanced I/O structure for versatile standards and interface

support

–

Up to 14,400 logic elements (LEs)

ꢀ

System-level features

Preliminary

Information

–

Up to four general-purpose phase-locked loops (PLLs) with

programmable multiplication and delay shifting

Up to 12 PLL output ports

Dedicated multiplier circuitry for high-speed implementation of

signed or unsigned multiplication up to 16 × 16

Embedded system blocks (ESBs) used to implement memory

functions including quad-port RAM, bidirectional dual-port

RAM, first-in first-out (FIFO) buffers, and content-addressable

memory (CAM)

–

Each ESB contains 4,096 bits and can be split and used as two

2,048-bit unidirectional dual-port RAM blocks

Table 1. Mercury Device Features

Feature

EP1M120

EP1M350

Typical gates

HSDI channels

LEs

120,000

350,000

4,800

14,400

ESBs (1)

Maximum RAM bits

Maximum user I/O pins

49,152

303

114,688

486

Note:

(1) Each ESB can be used for two dual- or single-port RAM blocks.

Altera Corporation

A-DS-MERCURY-01.1

12 3 4 5 6 7...84

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