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EP1M350FC780-5 PDF预览

EP1M350FC780-5

更新时间: 2024-09-23 15:38:15
品牌 Logo 应用领域
阿尔特拉 - ALTERA LTE输入元件可编程逻辑
页数 文件大小 规格书
84页 936K
描述
Loadable PLD, CMOS, PBGA780, 29 X 29 MM, 1 MM PITCH, FINE LINE, BGA-780

EP1M350FC780-5 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:HBGA,针数:780
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.76Is Samacsys:N
JESD-30 代码:S-PBGA-B780JESD-609代码:e1
长度:29 mm专用输入次数:
I/O 线路数量:486端子数量:780
最高工作温度:85 °C最低工作温度:
组织:0 DEDICATED INPUTS, 486 I/O输出函数:MACROCELL
封装主体材料:PLASTIC/EPOXY封装代码:HBGA
封装形状:SQUARE封装形式:GRID ARRAY, HEAT SINK/SLUG
可编程逻辑类型:LOADABLE PLD认证状态:Not Qualified
座面最大高度:3.5 mm最大供电电压:1.89 V
最小供电电压:1.71 V标称供电电压:1.8 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子面层:TIN SILVER COPPER
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM宽度:29 mm
Base Number Matches:1

EP1M350FC780-5 数据手册

 浏览型号EP1M350FC780-5的Datasheet PDF文件第2页浏览型号EP1M350FC780-5的Datasheet PDF文件第3页浏览型号EP1M350FC780-5的Datasheet PDF文件第4页浏览型号EP1M350FC780-5的Datasheet PDF文件第5页浏览型号EP1M350FC780-5的Datasheet PDF文件第6页浏览型号EP1M350FC780-5的Datasheet PDF文件第7页 
Mercury  
Programmable Logic  
Device Family  
®
February 2001, ver. 1.1  
Data Sheet  
High-performance programmable logic device (PLD) family (see  
Table 1)  
Features…  
Integrated high-speed transceivers with support for clock data  
recovery (CDR) at up to 1.25 gigabits per second (Gbps)  
Look-up table (LUT)-based architecture optimized for high  
speed  
Advanced interconnect structure for fast routing of critical paths  
Enhanced I/O structure for versatile standards and interface  
support  
Up to 14,400 logic elements (LEs)  
System-level features  
Preliminary  
Information  
Up to four general-purpose phase-locked loops (PLLs) with  
programmable multiplication and delay shifting  
Up to 12 PLL output ports  
Dedicated multiplier circuitry for high-speed implementation of  
signed or unsigned multiplication up to 16 × 16  
Embedded system blocks (ESBs) used to implement memory  
functions including quad-port RAM, bidirectional dual-port  
RAM, first-in first-out (FIFO) buffers, and content-addressable  
memory (CAM)  
Each ESB contains 4,096 bits and can be split and used as two  
2,048-bit unidirectional dual-port RAM blocks  
Table 1. Mercury Device Features  
Feature  
EP1M120  
EP1M350  
Typical gates  
HSDI channels  
LEs  
120,000  
8
350,000  
18  
4,800  
12  
14,400  
28  
ESBs (1)  
Maximum RAM bits  
Maximum user I/O pins  
49,152  
303  
114,688  
486  
Note:  
(1) Each ESB can be used for two dual- or single-port RAM blocks.  
Altera Corporation  
1
A-DS-MERCURY-01.1  

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