Datasheet > EMB12P03V

EMB12P03V

更新时间： 2024-11-02 17:15:27

品牌	Logo	应用领域
杰力科技 - EXCELLIANCE		/
页数	文件大小	规格书
7页	860K
描述
EDFN3X3

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中文翻译

获取价格

数据手册

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EMB12P03V 数据手册

EMB12P03V

P-Channel Logic Level Enhancement Mode Field Effect Transistor

Product Summary:

BVDSS

-30V

12mΩ

-21A

RDSON (MAX.)

P-Channel MOSFET

UIS, Rg 100% Tested

Pb-Free Lead Plating & Halogen Free

ABSOLUTE MAXIMUM RATINGS (T_A= 25 °C Unless Otherwise Noted)

PARAMETERS/TEST CONDITIONS

SYMBOL

LIMITS

±25

UNIT

Gate-Source Voltage

V_GS

T_C= 25 °C

-21

Continuous Drain Current

I_D

T_A= 25 °C

-12

-16

-84

-43

T_C= 100 °C

Pulsed Drain Current¹

I_DM

I_AS

Avalanche Current

L = 0.1mH, I_AS=-43A, RG=25Ω

L = 0.05mH

Avalanche Energy

E_AS

E_AR

Repetitive Avalanche Energy²

T_C= 25 °C

Power Dissipation

P_D

T_C= 100 °C

8.3

2.5

T_A= 25 °C

P_D

°C

T_A= 100 °C

Operating Junction & Storage Temperature Range

T_j, T_stg

-55 to 150

100% UIS testing in condition of V_D=-20V, L=0.1mH, V_G=-10V, I_L=-25A, Rated V_DS=-30V P-CH

THERMAL RESISTANCE RATINGS

THERMAL RESISTANCE

SYMBOL

R_JC

TYPICAL

MAXIMUM

UNIT

Junction-to-Case

Junction-to-Ambient³

°C / W

R_JA

¹Pulse width limited by maximum junction temperature.

²Duty cycle  1％

³50°C / W when mounted on a 1 in²pad of 2 oz copper.

2019/6/25

p.1

12 3 4 5 6 7

中文翻译

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