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EDI88257C/LP-C PDF预览

EDI88257C/LP-C

更新时间: 2024-11-01 23:50:07
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其他 - ETC 电池静态存储器
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6页 190K
描述
SRAM

EDI88257C/LP-C 数据手册

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EDI88257C  
HI-RELIABILITY PRODUCT  
256Kx8 Monolithic SRAM  
FEATURES  
The EDI88257C is a 2 Megabit 256Kx8 bit Monolithic CMOS Static  
RAM.  
256Kx8 CMOS Static  
Random Access Memory  
• Access Times of 70, 85, 100ns  
• Data Retention Function (LP Versions)  
• TTL Compatible Inputs and Outputs  
• Fully Static, No Clocks  
The 32 pin DIP pinout adheres to the JEDEC standard for the two  
megabit device, and is a pin replacement for the 256Kx8 module,  
EDI88257C. The device is upgradeable to the 512Kx8 SRAM, the  
EDI88512C. Pin 1 becomes the higher order address.  
A Low Power version, EDI88257LP, offers a data retention func-  
tion for battery back-up opperation. Military product is available  
compliant to Appendix A of MIL-PRF-38535.  
JEDEC Approved Pinout  
• 32 pin Ceramic DIP, 0.6 mils wide (Package 9)  
Single +5V (±10%) Supply Operation  
FIG. 1 PIN CONFIGURATION  
PIN DESCRIPTION  
32 DIP  
A0-17  
W
Address Inputs  
Write Enable  
TOP VIEW  
NC  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21 DQ  
20 DQ  
19 DQ  
18 DQ  
17 DQ  
VCC  
E
Chip Enable  
A
A
A
16  
14  
12  
A
15  
A
17  
G
Output Enable  
Data Inputs/Outputs  
Power (+5V ±10%)  
Ground  
W
DQ0-7  
VCC  
VSS  
NC  
A
A
7
6
5
4
3
2
1
A
A
A
A
13  
8
A
A
A
A
A
9
11  
G
BLOCK DIAGRAM  
Not Connected  
A
E
10  
A
DQ  
Ø
Ø
7
6
5
4
3
Memory Array  
DQ  
DQ  
1
2
V
SS 16  
Address  
Buffer  
Address  
Decoder  
I/O  
Circuits  
A
Ø-17  
DQØ-7  
W
E
G
1
September 1999 Rev. 2  
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com  

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