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EDI88257CA/LPA-C PDF预览

EDI88257CA/LPA-C

更新时间: 2024-11-01 23:50:07
品牌 Logo 应用领域
其他 - ETC 电池静态存储器
页数 文件大小 规格书
6页 125K
描述
SRAM

EDI88257CA/LPA-C 数据手册

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EDI88257CA  
HI-RELIABILITY PRODUCT  
256Kx8 Monolithic SRAM  
FEATURES  
The EDI88257CA is a 2 Megabit 256Kx8 bit Monolithic CMOS  
Static RAM.  
Access Times of 20, 25, 35, 45, 55ns  
Data Retention Function (LPA Versions)  
TTL Compatible Inputs and Outputs  
Fully Static, No Clocks  
The 32 pin DIP pinout adheres to the JEDEC evolutionary standard  
for the two megabit device. The device is upgradeable to the  
512Kx8 SRAM, the EDI88512CA. Pin 1 becomes the higher order  
address.  
Organized as 256Kx8  
A Low Power version, EDI88257LPA, offers a data retention  
function for battery back-up opperation. Military product is avail-  
able compliant to Appendix A of MIL-PRF-38535.  
Commercial, Industrial and Military Temperature Ranges  
JEDEC Approved Evolutionary Pinout  
• 32 pin Ceramic DIP, 0.6 mils wide (Package 9)  
Single +5V (±10%) Supply Operation  
FIG. 1 PIN CONFIGURATION  
PIN DESCRIPTION  
32 DIP  
I/O0-7  
A0-17  
WE  
CS  
Data Inputs/Outputs  
Address Inputs  
Write Enable  
TOP VIEW  
NC  
A16  
A14  
A12  
A7  
A6  
A5  
A4  
A3  
A2 10  
A1 11  
AØ 12  
I/OØ 13  
I/O1 14  
I/O2 15  
1
2
3
4
5
6
7
8
9
32 VCC  
31 A15  
30 A17  
29 WE  
28 A13  
27 A8  
Chip Selects  
OE  
Output Enable  
Power (+5V ±10%)  
Ground  
VCC  
VSS  
NC  
26 A9  
25 A11  
24 OE  
23 A10  
22 CS  
21 I/O7  
20 I/O6  
19 I/O5  
18 I/O4  
17 I/O3  
BLOCK DIAGRAM  
Not Connected  
Memory Array  
VSS 16  
Address  
Buffer  
Address  
Decoder  
I/O  
Circuits  
A
Ø-17  
I/OØ-7  
WE  
CS  
OE  
1
May 2000 Rev. 2  
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com  

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