Datasheet > EDI88257CA45CI

EDI88257CA45CI

更新时间： 2024-11-02 19:32:55

品牌	Logo	应用领域
美高森美 - MICROSEMI		静态存储器
页数	文件大小	规格书
8页	762K
描述
Standard SRAM, 256KX8, 45ns, CMOS, CDIP32, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-32

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EDI88257CA45CI 数据手册

EDI88257CA

256Kx8 Monolithic SRAM

FEATURES

 Access Times of 20, 25, 35, 45, 55ns

 Data Retention Function (LPA Versions)

 TTL Compatible Inputs and Outputs

 Fully Static, No Clocks

The EDI88257CA is a 2 Megabit 256Kx8 bit Monolithic CMOS

Static RAM.

The 32 pin DIP pinout adheres to the JEDEC evolutionary standard

for the two megabit device. The device is upgradeable to the

512Kx8 SRAM, the EDI88512CA. Pin 1 becomes the higher order

address.

 Organized as 256Kx8

 Commercial, Industrial and Military Temperature Ranges

 JEDEC Approved Evolutionary Pinout

• 32 pin Ceramic DIP, 0.6 mils wide (Package 9)

 Single +5V (±10%) Supply Operation

A Low Power version, EDI88257LPA, offers a data retention

function for battery back-up opperation. Military product is available

compliant to Appendix A of MIL-PRF-38535.

This product is subject to change without notice.

FIGURE 1 – PIN CONFIGURATION

PIN DESCRIPTION

I/O0-7

A0-17

WE#

CS#

OE#

V_CC

Data Inputs/Outputs

Address Inputs

Write Enable

32 DIP

TOP VIEW

Chip Selects

Output Enable

Power (+5V ±10%)

Ground

A16

A14

A12

32 V_CC

31 A15

30 A17

29 WE#

28 A13

27 A8

V_SS

Not Connected

BLOCK DIAGRAM

26 A9

25 A11#

24 OE

23 A10

22 CS#

21 I/O7

20 I/O6

19 I/O5

18 I/O4

17 I/O3

Memory Array

A2 10

A1 11

A0 12

I/O0 13

I/O1 14

I/O2 15

V_SS16

Address

Buffer

Address

Decoder

I/O

Circuits

A0-17

I/O0-7

WE#

OE#

Microsemi Corporation reserves the right to change products or speciﬁcations without notice.

Rev. 4

Microsemi Corporation • (602) 437-1520 • www.whiteedc.com

www.microsemi.com

12 3 4 5 6 7 8

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