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EDI88257LPA35CM PDF预览

EDI88257LPA35CM

更新时间: 2024-01-23 19:39:21
品牌 Logo 应用领域
WEDC 静态存储器内存集成电路
页数 文件大小 规格书
6页 293K
描述
Standard SRAM, 256KX8, 35ns, CMOS, CDIP32, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-32

EDI88257LPA35CM 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:0.600 INCH, SIDE BRAZED, CERAMIC, DIP-32Reach Compliance Code:unknown
风险等级:5.75最长访问时间:35 ns
I/O 类型:COMMONJESD-30 代码:R-CDIP-T32
长度:40.64 mm内存密度:2097152 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
功能数量:1端子数量:32
字数:262144 words字数代码:256000
工作模式:ASYNCHRONOUS最高工作温度:125 °C
最低工作温度:-55 °C组织:256KX8
输出特性:3-STATE封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:DIP封装等效代码:DIP32,.6
封装形状:RECTANGULAR封装形式:IN-LINE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
座面最大高度:3.937 mm最大待机电流:0.002 A
最小待机电流:2 V子类别:SRAMs
最大压摆率:0.2 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:15.24 mm

EDI88257LPA35CM 数据手册

 浏览型号EDI88257LPA35CM的Datasheet PDF文件第2页浏览型号EDI88257LPA35CM的Datasheet PDF文件第3页浏览型号EDI88257LPA35CM的Datasheet PDF文件第4页浏览型号EDI88257LPA35CM的Datasheet PDF文件第5页浏览型号EDI88257LPA35CM的Datasheet PDF文件第6页 
EDI88257CA  
White Electronic Designs  
256Kx8 Monolithic SRAM  
FEATURES  
The EDI88257CA is a 2 Megabit 256Kx8 bit Monolithic  
CMOS Static RAM.  
Access Times of 20, 25, 35, 45, 55ns  
Data Retention Function (LPA Versions)  
TTL Compatible Inputs and Outputs  
Fully Static, No Clocks  
The 32 pin DIP pinout adheres to the JEDEC evolutionary  
standard for the two megabit device. The device is  
upgradeable to the 512Kx8 SRAM, the EDI88512CA. Pin  
1 becomes the higher order address.  
Organized as 256Kx8  
ALow Power version, EDI88257LPA, offers a data retention  
function for battery back-up opperation. Military product is  
available compliant to Appendix A of MIL-PRF-38535.  
Commercial, Industrial and Military Temperature  
Ranges  
JEDEC Approved Evolutionary Pinout  
• 32 pin Ceramic DIP, 0.6 mils wide (Package 9)  
Single +5V ( 10ꢀ) Supply Operation  
This product is subject to change without notice.  
FIGURE 1 – PIN CONFIGURATION  
32 DIP  
TOP VIEW  
PIN DESCRIPTION  
I/O0-7  
A0-17  
WE#  
CS#  
OE#  
VCC  
Data Inputs/Outputs  
Address Inputs  
Write Enable  
NC  
A16  
A14  
A12  
A7  
1
2
3
4
5
6
7
8
9
32 VCC  
31 A15  
30 A17  
29 WE#  
28 A13  
27 A8  
Chip Selects  
Output Enable  
Power (+5V 10ꢀ%  
Ground  
A6  
A5  
26 A9  
VSS  
A4  
25 A11#  
24 OE  
A3  
NC  
Not Connected  
A2 10  
A1 11  
A0 12  
I/O0 13  
I/O1 14  
I/O2 15  
VSS 16  
23 A10  
22 CS#  
21 I/O7  
20 I/O6  
19 I/O5  
18 I/O4  
17 I/O3  
BLOCK DIAGRAM  
Memory Array  
Address  
Buffer  
Address  
Decoder  
I/O  
Circuits  
A
0-17  
I/O0-7  
WE#  
CS  
OE#  
White Electronic Designs Corp. reserves the right to change products or specifications without notice.  
May 2000  
Rev. 2  
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  

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