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EDI88257LP70CB PDF预览

EDI88257LP70CB

更新时间: 2024-11-03 10:26:47
品牌 Logo 应用领域
美高森美 - MICROSEMI 静态存储器内存集成电路
页数 文件大小 规格书
6页 285K
描述
Standard SRAM, 256KX8, 70ns, CMOS, CDIP32, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-32

EDI88257LP70CB 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Transferred零件包装代码:DIP
包装说明:0.600 INCH, SIDE BRAZED, CERAMIC, DIP-32针数:32
Reach Compliance Code:unknownECCN代码:3A001.A.2.C
HTS代码:8542.32.00.41风险等级:5.3
最长访问时间:70 nsI/O 类型:COMMON
JESD-30 代码:R-CDIP-T32内存密度:2097152 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
功能数量:1端子数量:32
字数:262144 words字数代码:256000
工作模式:ASYNCHRONOUS最高工作温度:125 °C
最低工作温度:-55 °C组织:256KX8
输出特性:3-STATE封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:DIP封装等效代码:DIP32,.6
封装形状:RECTANGULAR封装形式:IN-LINE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
筛选级别:MIL-STD-883 Class B最大待机电流:0.000185 A
最小待机电流:2 V子类别:SRAMs
最大压摆率:0.075 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10.16 mm

EDI88257LP70CB 数据手册

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EDI88257C  
White Electronic Designs  
256Kx8 Monolithic SRAM  
FEATURES  
256Kx8 CMOS Static  
The EDI88257C is a 2 Megabit 256Kx8 bit Monolithic  
CMOS Static RAM.  
Random Access Memory  
The 32 pin DIP pinout adheres to the JEDEC standard for  
the two megabit device, and is a pin replacement for the  
256Kx8 module, EDI88257C. The device is upgradeable  
to the 512Kx8 SRAM, the EDI88512C. Pin 1 becomes the  
higher order address.  
• Access Times of 70, 85, 100ns  
• Data Retention Function (LP Versions)  
• TTL Compatible Inputs and Outputs  
• Fully Static, No Clocks  
ALow Power version, EDI88257LP, offers a data retention  
function for battery back-up opperation. Military product is  
available compliant to Appendix A of MIL-PRF-38535.  
JEDEC Approved Pinout  
• 32 pin Ceramic DIP, 0.6 mils wide (Package 9)  
Single +5V ( 10ꢀ) Supply Operation  
FIGURE 1 – PIN CONFIGURATION  
32 DIP  
TOP VIEW  
PIN DESCRIPTION  
A0-17  
W#  
Address Inputs  
Write Enable  
NC  
A16  
A14  
A12  
A7  
A6  
A5  
A4  
A3  
A2 10  
A1 11  
A0 12  
DQ0 13  
DQ1 14  
DQ2 15  
VSS 16  
1
32 VCC  
31 A15  
30 A17  
29 W#  
28 A13  
27 A8  
E#  
Chip Enable  
2
3
4
5
6
7
8
9
G#  
Output Enable  
Data Inputs/Outputs  
Power (+5V 10ꢀ%  
Ground  
DQ0-7  
VCC  
VSS  
26 A9  
25 A11  
24 G#  
23 A10  
22 E#  
21 I/O7  
20 I/O6  
19 I/O5  
18 I/O4  
17 I/O3  
NC  
Not Connected  
BLOCK DIAGRAM  
Memory Array  
Address  
Buffer  
Address  
Decoder  
I/O  
Circuits  
A0-17  
DQ0-7  
W#  
E#  
G#  
White Electronic Designs Corp. reserves the right to change products or specifications without notice.  
September 1999  
Rev. 2  
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  

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