Datasheet > EDI88257LPA55CC

EDI88257LPA55CC

更新时间： 2024-11-03 05:23:43

品牌	Logo	应用领域
WEDC		静态存储器内存集成电路
页数	文件大小	规格书
6页	293K
描述
Standard SRAM, 256KX8, 55ns, CMOS, CDIP32, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-32

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EDI88257LPA55CC 数据手册

EDI88257CA

White Electronic Designs

256Kx8 Monolithic SRAM

FEATURES

The EDI88257CA is a 2 Megabit 256Kx8 bit Monolithic

CMOS Static RAM.

ꢀ

Access Times of 20, 25, 35, 45, 55ns

Data Retention Function (LPA Versions)

TTL Compatible Inputs and Outputs

Fully Static, No Clocks

The 32 pin DIP pinout adheres to the JEDEC evolutionary

standard for the two megabit device. The device is

upgradeable to the 512Kx8 SRAM, the EDI88512CA. Pin

1 becomes the higher order address.

Organized as 256Kx8

ALow Power version, EDI88257LPA, offers a data retention

function for battery back-up opperation. Military product is

available compliant to Appendix A of MIL-PRF-38535.

Commercial, Industrial and Military Temperature

Ranges

ꢀ

JEDEC Approved Evolutionary Pinout

• 32 pin Ceramic DIP, 0.6 mils wide (Package 9)

Single +5V ( 10ꢀ) Supply Operation

This product is subject to change without notice.

FIGURE 1 – PIN CONFIGURATION

32 DIP

TOP VIEW

PIN DESCRIPTION

I/O0-7

A0-17

WE#

CS#

OE#

V_CC

Data Inputs/Outputs

Address Inputs

Write Enable

A16

A14

A12

32 V_CC

31 A15

30 A17

29 WE#

28 A13

27 A8

Chip Selects

Output Enable

Power (+5V 10ꢀ%

Ground

26 A9

V_SS

25 A11#

24 OE

Not Connected

A2 10

A1 11

A0 12

I/O0 13

I/O1 14

I/O2 15

V_SS16

23 A10

22 CS#

21 I/O7

20 I/O6

19 I/O5

18 I/O4

17 I/O3

BLOCK DIAGRAM

Memory Array

Address

Buffer

Address

Decoder

I/O

Circuits

0-17

I/O0-7

WE#

OE#

White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice.

May 2000

Rev. 2

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 3 4 5 6

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