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EDI88257CA35CI PDF预览

EDI88257CA35CI

更新时间: 2024-11-02 21:22:39
品牌 Logo 应用领域
WEDC 静态存储器内存集成电路
页数 文件大小 规格书
6页 258K
描述
Standard SRAM, 256KX8, 35ns, CMOS, CDIP32, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-32

EDI88257CA35CI 数据手册

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EDI88257CA  
White Electronic Designs  
256Kx8 Monolithic SRAM  
FEATURES  
The EDI88257CA is a 2 Megabit 256Kx8 bit Monolithic  
CMOS Static RAM.  
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Access Times of 20, 25, 35, 45, 55ns  
Data Retention Function (LPA Versions)  
TTL Compatible Inputs and Outputs  
Fully Static, No Clocks  
The 32 pin DIP pinout adheres to the JEDEC evolutionary  
standard for the two megabit device. The device is  
upgradeable to the 512Kx8 SRAM, the EDI88512CA. Pin  
1 becomes the higher order address.  
Organized as 256Kx8  
ALow Power version, EDI88257LPA, offers a data retention  
function for battery back-up opperation. Military product is  
available compliant to Appendix A of MIL-PRF-38535.  
Commercial, Industrial and Military Temperature  
Ranges  
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JEDEC Approved Evolutionary Pinout  
• 32 pin Ceramic DIP, 0.6 mils wide (Package 9)  
Single +5V (±10%) Supply Operation  
This product is subject to change without notice.  
FIGURE 1 – PIN CONFIGURATION  
32 DIP  
PIN DESCRIPTION  
TOP VIEW  
I/O0-7  
A0-17  
WE#  
CS#  
OE#  
VCC  
Data Inputs/Outputs  
Address Inputs  
Write Enable  
NC  
A16  
A14  
A12  
A7  
1
2
3
4
5
6
7
8
9
32 VCC  
31 A15  
30 A17  
29 WE#  
28 A13  
27 A8  
Chip Selects  
Output Enable  
Power (+5V ±10%)  
Ground  
A6  
A5  
26 A9  
VSS  
A4  
25 A11#  
24 OE  
A3  
NC  
Not Connected  
A2 10  
A1 11  
A0 12  
I/O0 13  
I/O1 14  
I/O2 15  
VSS 16  
23 A10  
22 CS#  
21 I/O7  
20 I/O6  
19 I/O5  
18 I/O4  
17 I/O3  
BLOCK DIAGRAM  
Memory Array  
Address  
Buffer  
Address  
Decoder  
I/O  
Circuits  
A
0-17  
I/O0-7  
WE#  
CS  
OE#  
White Electronic Designs Corp. reserves the right to change products or specications without notice.  
May 2000  
Rev. 2  
1
White Electronic Designs Corporation • (602) 437-1520 •www.whiteedc.com  

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