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EDI2AG272129V85D1 PDF预览

EDI2AG272129V85D1

更新时间: 2024-01-02 01:57:18
品牌 Logo 应用领域
WEDC 内存集成电路静态存储器
页数 文件大小 规格书
11页 162K
描述
2 Megabyte Sync/Sync Burst, Small Outline DIMM

EDI2AG272129V85D1 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:SODIMM-144Reach Compliance Code:unknown
风险等级:5.87最长访问时间:8.5 ns
其他特性:FLOW-THROUGH ARCHITECTUREI/O 类型:COMMON
JESD-30 代码:R-XDMA-N144JESD-609代码:e4
内存密度:18874368 bit内存集成电路类型:SRAM MODULE
内存宽度:72功能数量:1
端子数量:144字数:262144 words
字数代码:256000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:256KX72输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:DIMM
封装等效代码:DIMM144,32封装形状:RECTANGULAR
封装形式:MICROELECTRONIC ASSEMBLY并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
认证状态:Not Qualified最大待机电流:0.3 A
最小待机电流:3.14 V子类别:SRAMs
最大压摆率:2.2 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3.14 V标称供电电压 (Vsup):3.3 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子面层:GOLD
端子形式:NO LEAD端子节距:0.8 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

EDI2AG272129V85D1 数据手册

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EDI2AG272129V  
White Electronic Designs  
ADVANCED*  
2 Megabyte Sync/Sync Burst, Small Outline DIMM  
DESCRIPTION  
FEATURES  
The EDI2AG272129VxxD1 is a Synchronous/  
Synchronous Burst SRAM, 72 position SO DIMM (144  
contacts) Module, organized as 2x128Kx72. The Module  
contains four (4) Synchronous Burst Ram Devices,  
packaged in the industry standard JEDEC 14mmx20mm  
TQFP placed on a Multilayer FR4 Substrate. The  
module architecture is defined as a Sync/Sycn Burst,  
Flow-Through, with support for sequential burst. This  
module provides High Performance, 2-1-1-1 accesses  
when used in Burst Mode, and used as a Synchronous  
Only Mode, provides a high performance cost advantage  
over BiCMOS aysnchronous device architectures.  
2x128Kx72 Synchronous, Synchronous Burst  
Flow-Through Architecture  
Sequential Burst MODE  
Clock Controlled Registered Bank Enables (E1#, E2#)  
Clock Controlled Byte Write Mode Enable (BWE#)  
Clock Controlled Byte Write Enables  
(BW1# - BW8#)  
Clock Controlled Registered Address  
Clock Controlled Registered Global Write (GW#)  
Aysnchronous Output Enable (G#)  
Internally self-timed Write  
Gold Lead Finish  
3.3V 1ꢀ0 Operation  
Access Speed(s): TKHQV=8.5, 9, 1ꢀ, 12ns  
Common Data I/O  
High Capacitance (3ꢀpf) drive, at rated Access Speed  
Single total array Clock  
Synchronous Only operations are performed via  
strapping ADSC# Low, and ADSP# / ADV# High, which  
provides for Ultra Fast Accesses in Read Mode while  
providing for internally self-timed Early Writes.  
Synchronous/Synchronous Burst operations are in  
relation to an externally supplied clock, Registered  
Address, Registered Global Write, Registered Enables  
as well as anAsynchronous Output enable. This Module  
has been defined with full flexibility, which allows  
individual control of each of the eight bytes, as well as  
Quad Words in both Read and Write Operations.  
Multiple Vcc and Gnd  
*This product is under development, is not qualified or characterized and is subject to  
change or cancellation without notice.  
White Electronic Designs Corp. reserves the right to change products or specifications without notice.  
July 1999  
Rev 1  
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  

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