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EDE2508ABSE-GE PDF预览

EDE2508ABSE-GE

更新时间: 2024-11-06 22:27:55
品牌 Logo 应用领域
尔必达 - ELPIDA 动态存储器双倍数据速率
页数 文件大小 规格书
66页 679K
描述
256M bits DDR2 SDRAM for HYPER DIMM

EDE2508ABSE-GE 数据手册

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PRELIMINARY DATA SHEET  
256M bits DDR2 SDRAM  
for HYPER DIMM  
EDE2508ABSE-GE (32M words × 8 bits)  
EDE2516ABSE-GE (16M words × 16 bits)  
Features  
Description  
The EDE2508ABSE is a 256M bits DDR2 SDRAM  
Power supply: VDD, VDDQ = 1.85V ± 0.1V  
organized as 8,388,608 words × 8 bits × 4 banks.  
It is packaged in 60-ball FBGA (µBGA) package.  
Double-data-rate architecture: two data transfers per  
clock cycle  
Bi-directional, differential data strobe (DQS and  
/DQS) is transmitted/received with data, to be used in  
capturing data at the receiver  
The EDE2516ABSE is a 256M bits DDR2 SDRAM  
organized as 4,194,304 words × 16 bits × 4 banks.  
It is packaged in 84-ball FBGA (µBGA) package.  
DQS is edge aligned with data for READs: center-  
aligned with data for WRITEs  
Differential clock inputs (CK and /CK)  
DLL aligns DQ and DQS transitions with CK  
transitions  
Commands entered on each positive CK edge: data  
and data mask referenced to both edges of DQS  
Four internal banks for concurrent operation  
Data mask (DM) for write data  
Burst lengths: 4, 8  
/CAS Latency (CL): 5  
Auto precharge operation for each burst access  
Auto refresh and self refresh modes  
Average refresh period  
7.8µs at 0°C TC ≤ +85°C  
3.9µs at +85°C < TC ≤ +95°C  
SSTL_18 compatible I/O  
Posted CAS by programmable additive latency for  
better command and data bus efficiency  
Off-Chip-Driver Impedance Adjustment and On-Die-  
Termination for better signal quality  
Programmable RDQS, /RDQS output for making × 8  
organization compatible to × 4 organization  
/DQS, (/RDQS) can be disabled for single-ended  
Data Strobe operation.  
FBGA (µBGA) package with lead free solder  
(Sn-Ag-Cu)  
Document No. E0657E20 (Ver. 2.0)  
Date Published May 2005 (K) Japan  
Printed in Japan  
URL: http://www.elpida.com  
Elpida Memory, Inc. 2005  

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