Datasheet > EDE2116AEBG

EDE2116AEBG

更新时间： 2024-11-07 11:44:35

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
73页	515K
描述
2G bits DDR2 SDRAM

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EDE2116AEBG 数据手册

DATA SHEET

2G bits DDR2 SDRAM

EDE2116AEBG (128M words × 16 bits)

Specifications

Features

• Density: 2G bits

• Double-data-rate architecture; two data transfers per

clock cycle

• Organization

• The high-speed data transfer is realized by the 4 bits

prefetch pipelined architecture

16M words × 16 bits × 8 banks

• Package

• Bi-directional differential data strobe (DQS and /DQS)

is transmitted/received with data for capturing data at

the receiver

84-ball FBGA

Lead-free (RoHS compliant) and Halogen-free

• Power supply: VDD, VDDQ = 1.8V ± 0.1V

• Data rate

• DQS is edge-aligned with data for READs; center-

aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

800Mbps (max.)

• DLL aligns DQ and DQS transitions with CK

• 2KB page size

transitions

Row address: A0 to A13

Column address: A0 to A9

• Eight internal banks for concurrent operation

• Interface: SSTL_18

• Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

• Data mask (DM) for write data

• Posted /CAS by programmable additive latency for

better command and data bus efficiency

• Burst lengths (BL): 4, 8

• Burst type (BT):

• /DQS can be disabled for single-ended Data Strobe

operation

Sequential (4, 8)

Interleave (4, 8)

• Off-Chip Driver (OCD) impedance adjustment is not

supported.

• /CAS Latency (CL): 3, 4, 5, 6

• Precharge: auto precharge option for each burst

access

• Driver strength: normal, weak

• Refresh: auto-refresh, self-refresh

• Refresh cycles: 8192 cycles/64ms

Average refresh period

7.8µs at 0°C ≤ TC ≤ +85°C

3.9µs at +85°C < TC ≤ +95°C

• Operating case temperature range

TC = 0°C to +95°C

Document No. E1820E21 (Ver.2.1)

Date Published November 2011 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2011

12 3 4 5 6 7...73

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