5秒后页面跳转
EDE2108AEBG-8E-F PDF预览

EDE2108AEBG-8E-F

更新时间: 2024-11-07 12:48:03
品牌 Logo 应用领域
尔必达 - ELPIDA /
页数 文件大小 规格书
73页 498K
描述
Lead-free (RoHS compliant) and Halogen-free

EDE2108AEBG-8E-F 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:TFBGA,针数:60
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.36风险等级:5.82
访问模式:MULTI BANK PAGE BURST最长访问时间:0.4 ns
其他特性:AUTO/SELF REFRESHJESD-30 代码:R-PBGA-B60
JESD-609代码:e1长度:9.5 mm
内存密度:2147483648 bit内存集成电路类型:DDR DRAM
内存宽度:8功能数量:1
端口数量:1端子数量:60
字数:268435456 words字数代码:256000000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:组织:256MX8
封装主体材料:PLASTIC/EPOXY封装代码:TFBGA
封装形状:RECTANGULAR封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH
座面最大高度:1.2 mm自我刷新:YES
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子面层:TIN SILVER COPPER端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
宽度:9 mmBase Number Matches:1

EDE2108AEBG-8E-F 数据手册

 浏览型号EDE2108AEBG-8E-F的Datasheet PDF文件第2页浏览型号EDE2108AEBG-8E-F的Datasheet PDF文件第3页浏览型号EDE2108AEBG-8E-F的Datasheet PDF文件第4页浏览型号EDE2108AEBG-8E-F的Datasheet PDF文件第5页浏览型号EDE2108AEBG-8E-F的Datasheet PDF文件第6页浏览型号EDE2108AEBG-8E-F的Datasheet PDF文件第7页 
DATA SHEET  
2G bits DDR2 SDRAM  
EDE2108AEBG (256M words 8 bits)  
Specifications  
Features  
Density: 2G bits  
Organization  
32M words 8 bits 8 banks  
Package  
60-ball FBGA  
Lead-free (RoHS compliant) and Halogen-free  
Power supply: VDD, VDDQ 1.8V 0.1V  
Data rate  
Double-data-rate architecture; two data transfers per  
clock cycle  
The high-speed data transfer is realized by the 4 bits  
prefetch pipelined architecture  
Bi-directional differential data strobe (DQS and /DQS)  
is transmitted/received with data for capturing data at  
the receiver  
DQS is edge-aligned with data for READs; center-  
aligned with data for WRITEs  
Differential clock inputs (CK and /CK)  
800Mbps (max.)  
DLL aligns DQ and DQS transitions with CK  
1KB page size  
transitions  
Row address: A0 to A14  
Column address: A0 to A9  
Eight internal banks for concurrent operation  
Interface: SSTL_18  
Burst lengths (BL): 4, 8  
Burst type (BT):  
Commands entered on each positive CK edge; data  
and data mask referenced to both edges of DQS  
Data mask (DM) for write data  
Posted /CAS by programmable additive latency for  
better command and data bus efficiency  
/DQS can be disabled for single-ended Data Strobe  
operation  
Sequential (4, 8)  
Interleave (4, 8)  
/CAS Latency (CL): 3, 4, 5, 6  
Off-Chip Driver (OCD) impedance adjustment is not  
supported.  
Precharge: auto precharge option for each burst  
access  
Driver strength: normal, weak  
Refresh: auto-refresh, self-refresh  
Refresh cycles: 8192 cycles/64ms  
Average refresh period  
7.8s at 0C TC  85C  
3.9s at 85C TC  95C  
Operating case temperature range  
TC = 0C to +95C  
Document No. E1950E11 (Ver.1.1)  
Date Published December 2012 (K) Japan  
Printed in Japan  
URL: http://www.elpida.com  
Elpida Memory, Inc. 2012  

与EDE2108AEBG-8E-F相关器件

型号 品牌 获取价格 描述 数据表
EDE2116ABSE ELPIDA

获取价格

2G bits DDR2 SDRAM
EDE2116ABSE-5C-E ELPIDA

获取价格

2G bits DDR2 SDRAM
EDE2116ABSE-6E-E ELPIDA

获取价格

2G bits DDR2 SDRAM
EDE2116ABSE-8G-E ELPIDA

获取价格

2G bits DDR2 SDRAM
EDE2116AEBG ELPIDA

获取价格

2G bits DDR2 SDRAM
EDE2116AEBG-8E-F ELPIDA

获取价格

2G bits DDR2 SDRAM
EDE2504AASE ELPIDA

获取价格

256M bits DDR2 SDRAM
EDE2504AASE-4A-E ELPIDA

获取价格

256M bits DDR2 SDRAM
EDE2504AASE-4C-E ELPIDA

获取价格

256M bits DDR2 SDRAM
EDE2504AASE-5C-E ELPIDA

获取价格

256M bits DDR2 SDRAM