EBD52UC8AMFA-5B

更新时间： 2024-10-28 06:55:27

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
18页	156K
描述
512MB Unbuffered DDR SDRAM DIMM

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中文翻译

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技术参数
数据手册

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EBD52UC8AMFA-5B 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	DIMM	包装说明：	DIMM, DIMM184
针数：	184	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.32.00.36
风险等级：	5.92	访问模式：	DUAL BANK PAGE BURST
最长访问时间：	0.7 ns	其他特性：	AUTO/SELF REFRESH
最大时钟频率 (fCLK)：	200 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-XDMA-N184	JESD-609代码：	e0
内存密度：	4294967296 bit	内存集成电路类型：	DDR DRAM MODULE
内存宽度：	64	功能数量：	1
端口数量：	1	端子数量：	184
字数：	67108864 words	字数代码：	64000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	64MX64
输出特性：	3-STATE	封装主体材料：	UNSPECIFIED
封装代码：	DIMM	封装等效代码：	DIMM184
封装形状：	RECTANGULAR	封装形式：	MICROELECTRONIC ASSEMBLY
峰值回流温度（摄氏度）：	235	电源：	2.6 V
认证状态：	Not Qualified	刷新周期：	8192
自我刷新：	YES	最大待机电流：	0.16 A
子类别：	DRAMs	最大压摆率：	2.76 mA
最大供电电压 (Vsup)：	2.7 V	最小供电电压 (Vsup)：	2.5 V
标称供电电压 (Vsup)：	2.6 V	表面贴装：	NO
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	NO LEAD
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	Base Number Matches：	1

EBD52UC8AMFA-5B 数据手册

EBD52UC8AMFA-5

Pin Functions

CK, /CK (input pin)

The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross

point of the CK rising edge and the VREF level. When a read operation, DQSs and DQs are referred to the cross

point of the CK and the /CK. When a write operation, DMs and DQs are referred to the cross point of the DQS and

the VREF level. DQSs for write operation are referred to the cross point of the CK and the /CK.

/CS (input pin)

When /CS is low, commands and data can be input. When /CS is high, all inputs are ignored. However, internal

operations (bank active, burst operations, etc.) are held.

/RAS, /CAS, and /WE (input pins)

These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels.

See "Command operation".

A0 to A12 (input pins)

Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the

VREF level in a bank active command cycle. Column address (AY0 to AY9) is loaded via the A0 to the A9 at the

cross point of the CK rising edge and the VREF level in a read or a write command cycle. This column address

becomes the starting address of a burst operation.

A10 (AP) (input pin)

A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If

A10 = high when a precharge command is issued, all banks are precharged. If A10 = low when a precharge

command is issued, only the bank that is selected by BA1, BA0 is precharged. If A10 = high when read or write

command, auto-precharge function is enabled. While A10 = low, auto-precharge function is disabled.

BA0, BA1 (input pin)

BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See

Bank Select Signal Table)

[Bank Select Signal Table]

BA0

BA1

Bank 0

Bank 1

Bank 2

Bank 3

Remark: H: VIH. L: VIL.

CKE (input pin)

CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the

CKE is driven low and exited when it resumes to high.

The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge

and the VREF level with proper setup time tIS, at the next CK rising edge CKE level must be kept with proper hold

time tIH.

DQ (input and output pins)

Data are input to and output from these pins.

DQS (input and output pin)

DQS provide the read data strobes (as output) and the write data strobes (as input).

Preliminary Data Sheet E0455E10 (Ver. 1.0)

1...11 12 131415 16 17 18

中文翻译

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与EBD52UC8AMFA-5B相关器件

型号	品牌	获取价格	描述	数据表
EBD52UC8AMFA-5B-E	ELPIDA	获取价格	暂无描述
EBD52UC8AMFA-6B	ELPIDA	获取价格	512MB Unbuffered DDR SDRAM DIMM
EBD52UD6ADSA	ELPIDA	获取价格	512MB DDR SDRAM SO-(64M words x 64 bits, 2 Ranks)
EBD52UD6ADSA-6B	ELPIDA	获取价格	512MB DDR SDRAM SO-(64M words x 64 bits, 2 Ranks)
EBD52UD6ADSA-6B-E	ELPIDA	获取价格	512MB DDR SDRAM SO-DIMM (64M words x 64 bits, 2 Ranks)
EBD52UD6ADSA-7A	ELPIDA	获取价格	512MB DDR SDRAM SO-(64M words x 64 bits, 2 Ranks)
EBD52UD6ADSA-7A-E	ELPIDA	获取价格	512MB DDR SDRAM SO-DIMM (64M words x 64 bits, 2 Ranks)
EBD52UD6ADSA-7B	ELPIDA	获取价格	512MB DDR SDRAM SO-(64M words x 64 bits, 2 Ranks)
EBD52UD6ADSA-7B-E	ELPIDA	获取价格	512MB DDR SDRAM SO-DIMM (64M words x 64 bits, 2 Ranks)
EBD52UD6ADSA-E	ELPIDA	获取价格	512MB DDR SDRAM SO-DIMM (64M words x 64 bits, 2 Ranks)

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