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EBD64UB6ALF-7A PDF预览

EBD64UB6ALF-7A

更新时间: 2024-10-28 21:14:35
品牌 Logo 应用领域
尔必达 - ELPIDA 时钟动态存储器双倍数据速率内存集成电路
页数 文件大小 规格书
16页 147K
描述
DDR DRAM Module, 8MX64, 0.75ns, CMOS, DIMM-184

EBD64UB6ALF-7A 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIMM包装说明:DIMM, DIMM184
针数:184Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.28
风险等级:5.92访问模式:SINGLE BANK PAGE BURST
最长访问时间:0.75 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):133 MHzI/O 类型:COMMON
JESD-30 代码:R-XDMA-N184内存密度:536870912 bit
内存集成电路类型:DDR DRAM MODULE内存宽度:64
湿度敏感等级:1功能数量:1
端口数量:1端子数量:184
字数:8388608 words字数代码:8000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:8MX64
输出特性:3-STATE封装主体材料:UNSPECIFIED
封装代码:DIMM封装等效代码:DIMM184
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
峰值回流温度(摄氏度):225电源:2.5 V
认证状态:Not Qualified刷新周期:4096
自我刷新:YES子类别:DRAMs
最大供电电压 (Vsup):2.7 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):2.5 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子形式:NO LEAD端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

EBD64UB6ALF-7A 数据手册

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PRELIMINARY DATA SHEET  
64MB Unbuffered DDR SDRAM DIMM  
EBD64UB6ALF (8M words × 64 bits, 1 Bank)  
Description  
Features  
The EBD64UB6ALF is 8M words × 64 bits, 1 bank  
Double Data Rate (DDR) SDRAM unbuffered module,  
184-pin socket type dual in line memory module  
(DIMM)  
mounted  
4 pieces of 128M bits DDR SDRAM  
Outline: 133.35mm (Length) × 31.75mm (Height) ×  
(EDD1216ALTA) sealed in TSOP package. Read and  
write operations are performed at the cross points of  
the CLK and the /CLK. This high-speed data transfer  
is realized by the 2 bits prefetch-pipelined architecture.  
Data strobe (DQS) both for read and write are available  
for high speed and reliable data bus design. By setting  
extended mode register, the on-chip Delay Locked  
Loop (DLL) can be set enable or disable. An outline of  
the products is 184-pin socket type package (dual lead  
out). Therefore, it makes high density mounting  
possible without surface mount technology. It provides  
4.00mm (Thickness)  
Lead pitch: 1.27mm  
2.5V power supply (VDD/VDDQ)  
SSTL-2 interface for all inputs and outputs  
Clock frequency: 133MHz/100MHz (max.)  
Data inputs and outputs are synchronized with DQS  
4 banks can operate simultaneously and  
independently (Component)  
Burst read/write operation  
Programmable burst length: 2, 4, 8  
Burst read stop capability  
Programmable burst sequence  
Sequential  
common data inputs and outputs.  
Decoupling  
capacitors are mounted beside each TSOP on the  
module board.  
Interleave  
Start addressing capability  
Even and Odd  
Programmable /CAS latency (CL): 2, 2.5  
8192 refresh cycles: 15.6µs (4096/64ms)  
2 variations of refresh  
Auto refresh  
Self refresh  
Document No. E0217E10 (Ver. 1.0)  
Date Published September 2001 (K)  
Printed in Japan  
URL: http://www.elpida.com  
C
Elpida Memory, Inc. 2001  
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.  

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