Datasheet > DTC114EM3/D

DTC114EM3/D

更新时间： 2022-01-19 07:47:00

品牌	Logo	应用领域
其他 - ETC		晶体数字晶体管
页数	文件大小	规格书
10页	93K
描述
Digital Transistors

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数据手册

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DTC114EM3/D 数据手册

DTC114EM3T5G Series

Digital Transistors (BRT)

NPN Silicon Surface Mount Transistors

with Monolithic Bias Resistor Network

This new series of digital transistors is designed to replace a single

device and its external resistor bias network. The digital transistor

contains a single transistor with a monolithic bias network consisting

of two resistors; a series base resistor and a base−emitter resistor. The

digital transistor eliminates these individual components by

integrating them into a single device. The use of a digital transistor can

reduce both system cost and board space. The device is housed in the

SOT−723 package which is designed for low power surface mount

applications.

http://onsemi.com

NPN SILICON

DIGITAL

TRANSISTORS

• Simplifies Circuit Design

• Reduces Board Space

• Reduces Component Count

• The SOT−723 Package can be Soldered using Wave or Reflow.

• Available in 4 mm, 8000 Unit Tape & Reel

• These are Pb−Free Devices

PIN 3

COLLECTOR

(OUTPUT)

PIN 1

BASE

(INPUT)

PIN 2

EMITTER

(GROUND)

MAXIMUM RATINGS (T = 25°C unless otherwise noted)

Rating

Collector-Base Voltage

Collector-Emitter Voltage

Collector Current

Symbol

Value

Unit

Vdc

MARKING

DIAGRAM

CBO

CEO

Vdc

100

mAdc

XX M

CASE 631AA

SOT−723

Style 1

XX= Specific Device Code

(See Marking Table on page 2)

M = Date Code

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page of this data sheet.

Semiconductor Components Industries, LLC, 2004

Publication Order Number:

February, 2004 − Rev. 0

DTC114EM3/D

12 3 4 5 6 7...10

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