Datasheet > DTC114EM3T5G_11

DTC114EM3T5G_11

更新时间： 2024-11-28 09:58:15

品牌	Logo	应用领域
安森美 - ONSEMI		晶体数字晶体管
页数	文件大小	规格书
11页	121K
描述
Digital Transistors

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DTC114EM3T5G_11 数据手册

DTC114EM3T5G Series

Digital Transistors (BRT)

NPN Silicon Surface Mount Transistors

with Monolithic Bias Resistor Network

This new series of digital transistors is designed to replace a single

device and its external resistor bias network. The digital transistor

contains a single transistor with a monolithic bias network consisting

of two resistors; a series base resistor and a base−emitter resistor. The

digital transistor eliminates these individual components by

integrating them into a single device. The use of a digital transistor can

reduce both system cost and board space. The device is housed in the

SOT−723 package which is designed for low power surface mount

applications.

http://onsemi.com

NPN SILICON DIGITAL

TRANSISTORS

PIN 3

COLLECTOR

(OUTPUT)

Features

PIN 1

BASE

(INPUT)

• Simplifies Circuit Design

• Reduces Board Space

• Reduces Component Count

PIN 2

EMITTER

(GROUND)

• The SOT−723 Package can be Soldered using Wave or Reflow.

• Available in 4 mm, 8000 Unit Tape & Reel

• These are Pb−Free Devices

MAXIMUM RATINGS (T = 25°C unless otherwise noted)

SOT−723

CASE 631AA

STYLE 1

Rating

Collector-Base Voltage

Collector-Emitter Voltage

Collector Current

Symbol

Value

Unit

Vdc

CBO

CEO

Vdc

100

mAdc

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

MARKING DIAGRAM

xx = Specific Device Code

(See Marking Table on page 2)

M = Date Code

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

Publication Order Number:

March, 2011 − Rev. 4

DTC114EM3/D

12 3 4 5 6 7...11

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