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DS92LX2121_14

更新时间: 2024-09-26 02:58:19
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描述
10 - 50 MHz DC-Balanced Channel Link III Bi-Directional Control Serializer and Deserializer

DS92LX2121_14 数据手册

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DS92LX2121, DS92LX2122  
www.ti.com  
SNLS330I MAY 2010REVISED APRIL 2013  
DS92LX2121/DS92LX2122 10 - 50 MHz DC-Balanced Channel Link III Bi-Directional Control  
Serializer and Deserializer  
Check for Samples: DS92LX2121, DS92LX2122  
1
FEATURES  
APPLICATIONS  
2
General  
Industrial Displays, Touch Screens  
Medical Imaging  
Up to 1050 Mbits/sec Data Throughput  
10 MHz to 50 MHz Input Clock Support  
DESCRIPTION  
The DS92LX2121/DS92LX2122 chipset offers  
Supports 18-bit Color Depth (RGB666 + HS,  
VS, DE)  
a
Channel Link III interface with a high-speed forward  
channel and a full-duplex control channel for data  
transmission over a single differential pair. The  
DS92LX2121/DS92LX2122 incorporates differential  
signaling on both the high-speed and bi-directional  
back channel control data paths. The Serializer/  
Deserializer pair is targeted for direct connections  
between graphics host controller and displays  
modules. This chipset is ideally suited for driving  
video data to displays requiring 18-bit color depth  
(RGB666 + HS, VS, and DE) along with a bi-  
directional back channel control bus. The primary  
transport converts 21 bit data over a single high-  
speed serial stream, along with a separate low  
latency bi-directional back channel transport that  
accepts control information from an I2C port. Using  
TI’s embedded clock technology allows transparent  
full-duplex communication over a single differential  
pair, carrying asymmetrical bi-directional back  
channel control information in both directions. This  
single serial stream simplifies transferring a wide data  
bus over PCB traces and cable by eliminating the  
skew problems between parallel data and clock  
paths. This significantly saves system cost by  
narrowing data paths that in turn cable width,  
connector size and pins.  
Embedded Clock with DC Balanced Coding  
to Support AC-Coupled Interconnects  
Capable to Drive up to 10 Meters Shielded  
Twisted-Pair  
Bi-Directional Control Interface Channel  
with I2C Support  
I2C Interface for Device Configuration.  
Single-Pin ID Addressing  
Up to 4 GPI on DES and GPO on SER  
AT-SPEED BIST Diagnosis Feature to  
Validate Link Integrity  
Individual Power-Down Controls for both  
SER and DES  
User-Selectable Clock Edge for Parallel  
Data on both SER and DES  
Integrated Termination Resistors  
1.8V- or 3.3V-Compatible Parallel Bus  
Interface  
Single Power Supply at 1.8V  
IEC 61000–4–2 ESD Compliant  
Temperature Range 40°C to +85°C  
DESERIALIZER — DS92LX2122  
In addition, the Deserializer provides input  
equalization to compensate for loss from the media  
over longer distances. Internal DC balanced  
encoding/decoding is used to support AC-Coupled  
interconnects.  
No Reference Clock Required on  
Deserializer  
Programmable Receive Equalization  
LOCK Output Reporting Pin to Ensure  
EMI/EMC Mitigation  
A sleep function provides a power-savings mode  
when the high speed forward channel and embedded  
bi-directional control channel are not needed.  
Programmable Spread Spectrum (SSCG)  
Outputs  
The Serializer is offered in a 40-pin lead in WQFN  
and Deserializer is offered in a 48-pin WQFN  
packages.  
Receiver Output Drive Strength Control  
(RDS)  
Receiver Staggered Outputs  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2010–2013, Texas Instruments Incorporated  

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