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DS92UT16TUF/NOPB PDF预览

DS92UT16TUF/NOPB

更新时间： 2024-09-25 19:55:43
品牌 Logo 应用领域
德州仪器 - TI 接口集成电路
页数 文件大小 规格书
111页 2002K
描述
SPECIALTY INTERFACE CIRCUIT, PBGA196

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DS92UT16TUF/NOPB 技术参数

是否Rohs认证： 符合生命周期：Obsolete
包装说明：LBGA,Reach Compliance Code：compliant
风险等级：5.81接口集成电路类型：INTERFACE CIRCUIT
JESD-30 代码：S-PBGA-B196JESD-609代码：e1
长度：15 mm湿度敏感等级：3
功能数量：1端子数量：196
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装形状：SQUARE封装形式：GRID ARRAY, LOW PROFILE
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1.47 mm最大供电电压：2.63 V
最小供电电压：2.37 V标称供电电压：2.5 V
电源电压1-最大：3.6 V电源电压1-分钟：3 V
电源电压1-Nom：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：40宽度：15 mm
Base Number Matches：1

DS92UT16TUF/NOPB 数据手册

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OBSOLETE  
DS92UT16  
www.ti.com  
SNOS992E –JANUARY 2002–REVISED APRIL 2013  
DS92UT16 UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers  
Check for Samples: DS92UT16  
1
FEATURES  
•
Embedded Bidirectional, Non-Blocking Flow  
Control Over Serial Link for per MPHY Back  
Pressure  
23  
•
832 Mbps LVDS 16-bit Serializer and  
Deserializer Interface  
•
•
No External Memories Required  
–
–
–
–
–
Suitable for Cable, Printed Circuit Board,  
and Backplane Transmission Paths  
Embedded OAM Channel Over Serial Link  
–
–
–
Remote Alarm/Status Indications  
Link Trace Label  
10m Cable at Max LVDS Data Rate and  
Greater than 16m at Min LVDS Data Rate  
Embedded Clock With Random Data Lock  
Capability for Clock Recovery  
PRBS (x31 + x28 + 1) Based LVDS Link BER  
Test Facility  
Embedded Control Channel With Flow  
Control for Software Communication  
–
–
BIP16 Based Error Performance Monitoring  
In Protected Systems, the Standby Link  
OAM Channel is Available for Embedded  
Communications and Performance/Alarm  
Monitoring  
Two Independent LVDS Receiver Serial  
Ports for Optional 1:1 Protection  
–
–
Main and Redundant LVDS Transmit Ports  
•
•
Multiple Loop-Back Options  
Loop Timing Capability Enables LVDS  
Recovered Clock to Internally Drive LVDS  
Transmit Clock  
Standard Microprocessor Interface (Intel and  
Motorola Compatible)  
IEEE 1149.1 JTAG® Port  
–
Internal Buffers Allow Maximum LVDS  
Serial Bit Rate Independent of UTOPIA  
Clock Rate  
•
•
•
•
Temperature Range: −40°C to +85°C  
CMOS Technology for Low Power  
•
Programmable UTOPIA Interface  
LVDS Transceiver Section uses 3.3V Power  
Supply. Digital UTOPIA Section uses 2.5V  
Power Supply. All I/O are 3.3V Tolerant.  
–
–
–
UTOPIA Level 2 Up To 52 MHz  
ATM Layer or PHY Layer Interface  
ATM Layer Interface Can Support Up To  
248 Standard Level 2 PHY Ports With no  
Additional External Circuitry. Configured as  
31 MPHY’s, each With Up To 8 Sub-Ports  
•
196 LBGA Package, 15x15x1.37 mm, 1.0 mm  
Ball Pitch  
–
–
Supports Extended Cell Size Up To 64  
Bytes  
Supports 16- or 8-Bit Data Buses With  
Parity  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
3
JTAG is a registered trademark of JTAG.  
All other trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2002–2013, Texas Instruments Incorporated  
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