Datasheet > DS92LX2121

DS92LX2121

更新时间： 2024-11-13 09:56:59

品牌	Logo	应用领域
美国国家半导体 - NSC		/
页数	文件大小	规格书
10页	248K
描述
10 - 50 MHz Channel Link III Serializer and Deserializer with Embedded Bi-Directional Control Channel

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DS92LX2121 数据手册

ADVANCE

INFORMATION

DS92LX2121 / DS92LX2122

June 1, 2010

10 - 50 MHz Channel Link III Serializer and Deserializer with

Embedded Bi-Directional Control Channel

General Description

Features

The DS92LX2121/DS92LX2122 chipset offers a Channel

Link III interface to deliver clock, high-speed data and a low-

speed, bidirectional I2C control bus over a single twisted wire

pair. This single serial stream simplifies transferring a wide

data bus over PCB traces and cable by eliminating clock to

data skew, while reducing cable width and connector size.

The DS92LX2121/DS92LX2122 incorporates differential sig-

naling on both the high-speed and bi-directional back channel

control data paths.

Up to 1050 Mbits/sec data throughput

■

10 MHz to 50 MHz input clock support

Supports 18-bit color depth (RGB666 + HS, VS, DE)

Embedded clock with DC Balanced coding to support AC-

coupled interconnects

Capable to drive up to 10 meters shielded twisted-pair

Bi-directional control interface channel with I²C support

I²C interface for device configuration. Single-pin ID

addressing

■

The Serializer/ Deserializer pair is ideally suited for driving

video data with up to 18-bit color depth (RGB666 + HS, VS,

and DE) along with a bi-directional back channel control bus.

Up to 4 GPI on DES and GPO on SER

■

AT-SPEED BIST diagnosis feature to validate link integrity

In addition, the Deserializer provides input equalization to

compensate for loss from the media over longer distances.

Internal DC balanced encoding/decoding is used to support

AC-Coupled interconnects. Deserializer features such as out-

put slew rate control, spread spectrum clock generation and

staggered outputs can be enabled to lower EMI.

Individual power-down controls for both SER and DES

User-selectable clock edge for parallel data on both SER

and DES

Integrated termination resistors

■

1.8V- or 3.3V-compatible parallel bus interface

A sleep function provides a power-savings mode when the

high speed forward channel and embedded bi-directional

control channel are not needed.

Single power supply at 1.8V

IEC 61000–4–2 ESD compliant

Temperature range −40°C to +85°C

The Serializer is offered in a 40-pin lead in LLP and Deseri-

alizer is offered in a 48-pin LLP packages.

No reference clock required on Deserializer

Programmable Receive Equalization

LOCK output reporting pin to ensure

EMI/EMC Mitigation

■

DES Programmable Spread Spectrum (SSCG)

outputs

—

DES Receiver Output clock and data slew rate select

DES Receiver staggered outputs

—

Applications

Industrial Displays, Touch Screens

■

Medical Imaging

Typical Application Diagram

30125127

TRI-STATE® is a registered trademark of National Semiconductor Corporation.

301251

www.national.com

12 3 4 5 6 7...10

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与DS92LX2121相关器件

型号	品牌	获取价格	描述	数据表
DS92LX2121_14	TI	获取价格	10 - 50 MHz DC-Balanced Channel Link III Bi-Directional Control Serializer and Deserialize
DS92LX2121SQ/NOPB	TI	获取价格	10MHz 至 50MHz 直流平衡 Channel Link III 双向控制串行器 \|
DS92LX2121SQE/NOPB	ROCHESTER	获取价格	LINE DRIVER, QCC40, 6 X 6 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, LLP-40
DS92LX2121SQE/NOPB	TI	获取价格	10MHz 至 50MHz 直流平衡 Channel Link III 双向控制串行器 \|
DS92LX2121SQX/NOPB	TI	获取价格	10MHz 至 50MHz 直流平衡 Channel Link III 双向控制串行器 \|
DS92LX2122	TI	获取价格	DS92LX2121/DS92LX2122 10 - 50 MHz DC-Balanced Channel Link III Bi-Directional Control Seri
DS92LX2122	NSC	获取价格	10 - 50 MHz Channel Link III Serializer and Deserializer with Embedded Bi-Directional Cont
DS92LX2122SQ/NOPB	TI	获取价格	10 - 50MHz 直流平衡信道链路 III 双向控制解串器 \| RHS \| 48 \|
DS92LX2122SQE/NOPB	NSC	获取价格	IC LINE RECEIVER, QCC48, 6 X 6 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, LLP-48, Line Driver or R
DS92LX2122SQE/NOPB	TI	获取价格	10 - 50MHz 直流平衡信道链路 III 双向控制解串器 \| RHS \| 48 \|

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