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DS92LV0421SQE/NOPB PDF预览

DS92LV0421SQE/NOPB

更新时间： 2024-01-01 14:19:18
品牌 Logo 应用领域
德州仪器 - TI 驱动接口集成电路
页数 文件大小 规格书
58页 1257K
描述
具有 LVDS 并行接口的 10MHz 至 75MHz Channel-Link II 串行器 | NJK | 36 | -40 to 85

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DS92LV0421SQE/NOPB 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：QFN
包装说明：LLP-36针数：36
Reach Compliance Code：compliantECCN代码：5A991.B.1
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.22Is Samacsys：N
差分输出：YES驱动器位数：24
输入特性：DIFFERENTIAL接口集成电路类型：LINE DRIVER
接口标准：I2CJESD-30 代码：S-XQCC-N36
JESD-609代码：e3长度：6 mm
湿度敏感等级：3功能数量：1
端子数量：36最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装等效代码：LCC36,.25SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260电源：1.8,3.3 V
认证状态：Not Qualified最大接收延迟：
座面最大高度：0.8 mm子类别：Line Driver or Receivers
最大压摆率：100 mA最大供电电压：1.89 V
最小供电电压：1.71 V标称供电电压：1.8 V
电源电压1-最大：1.89 V电源电压1-分钟：1.71 V
电源电压1-Nom：1.8 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：6 mmBase Number Matches：1

DS92LV0421SQE/NOPB 数据手册

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DS92LV0421, DS92LV0422  
www.ti.com  
NAME  
SNLS325D –MAY 2010–REVISED DECEMBER 2016  
Pin Functions: DS92LV0421 (continued)  
PIN  
TYPE(1)  
DESCRIPTION(2)  
NO.  
CONTROL AND CONFIGURATION  
Operating Modes: Pin or Register Control, LVCMOS with pulldown.  
Determines the device operating mode and interfacing device (see Table 10).  
CONFIG[1:0] = 00: Interfacing to DS92LV2422 or DS92LV0422, Control Signal Filter DISABLED  
CONFIG[1:0] = 01: Interfacing to DS92LV2422 or DS92LV0422, Control Signal Filter ENABLED  
CONFIG [1:0] = 10: Interfacing to DS90UR124, DS99R124Q-Q1  
CONFIG[1:0]  
10, 9  
I
CONFIG [1:0] = 11: Interfacing to DS90C124  
De-emphasis Control: Pin or Register Control, Analog with pullup.  
De-emphasis = Open (float) - disabled  
To enable De-emphasis, tie a resistor from this pin to Ground or control through register (see  
Table 2).  
DE-EMPH  
MAPSEL  
19  
26  
I
I
Channel Link Map Select: Pin or Register Control, LVCMOS with pulldown.  
MAPSEL = 1, MSB on RXIN3± (see Figure 23).  
MAPSEL = 0, LSB on RXIN3± (see Figure 24).  
Power-down Mode input, LVCMOS with pulldown.  
PDB = 1, serializer is enabled (normal operation).  
See Power Supply Recommendations for more information.  
PDB = 0, serializer is powered down  
PDB  
23  
I
When the serializer is in the power-down state, the driver outputs (DOUT±) are both logic high,  
the PLL is shut down, and IDD is minimized. Control Registers are RESET.  
25, 3, 36,  
27, 18, 13,  
12, 8  
RES[7:0]  
VODSEL  
I
I
Reserved (tie low), LVCMOS with pulldown.  
Differential Driver Output Voltage Select: Pin or Register Control, LVCMOS with pulldown.  
VODSEL = 1, CML VOD is ±450 mV, 900 mVp-p (typical): long cable or de-emphasis  
applications  
20  
VODSEL = 0, CML VOD is ±300 mV, 600 mVp-p (typical): short cable (no de-emphasis), low  
power mode  
OPTIONAL BIST MODE  
BISTEN 21  
BIST Mode: Optional, LVCMOS with pulldown.  
BISTEN = 1, BIST is enabled  
I
BISTEN = 0, BIST is disabled (normal operation)  
OPTIONAL SERIAL BUS CONTROL  
Serial Control Bus Device ID Address Select: Optional, Analog  
Resistor to Ground and 10-kΩ pullup to 1.8-V rail (see Table 8).  
ID[X]  
SCL  
SDA  
4
6
7
I
I
Serial Control Bus Clock Input: Optional, LVCMOS (open-drain)  
SCL requires an external pullup resistor to VDDIO  
Serial Control Bus Data Input or Output: Optional, LVCMOS (open-drain)  
SDA requires an external pullup resistor VDDIO  
.
I/O  
.
POWER AND GROUND(3)  
DAP is the large metal contact at the bottom side, located at the center of the WQFN package.  
Connect to the ground plane (GND) with at least 9 vias.  
DAP  
GND  
G
VDDHS  
VDDIO  
VDDL  
14  
22  
5
P
P
P
P
P
P
TX high-speed logic power, 1.8 V ±5%  
LVCMOS I/O power and Channel Link I/O power, 1.8 V ±5% or 3.3 V ±10%  
Logic power, 1.8 V ±5%  
VDDP  
11  
24  
17  
PLL power, 1.8 V ±5%  
VDDRX  
VDDTX  
RX power, 1.8 V ±5%  
Output driver power, 1.8 V ±5%  
(3) The VDD (VDDn and VDDIO) supply ramp must be faster than 1.5 ms with a monotonic rise. If slower than 1.5 ms, a capacitor on the PDB  
pin is required to ensure PDB arrives after all the VDD supplies have settled to the recommended operating voltage.  
Copyright © 2010–2016, Texas Instruments Incorporated  
Submit Documentation Feedback  
5
Product Folder Links: DS92LV0421 DS92LV0422  
12345678...58

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