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DS92LV0422

更新时间: 2024-09-30 11:13:59
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德州仪器 - TI /
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描述
具有 LVDS 并行接口的 10 - 75MHz Channel Link II 解串器

DS92LV0422 数据手册

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DS92LV0421, DS92LV0422  
SNLS325D MAY 2010REVISED DECEMBER 2016  
DS92LV042x 10-MHz to-75 MHz Channel Link II Serializer and Deserializer  
With LVDS Parallel Interface  
1 Features  
3 Description  
The DS92LV042x chipset translates a Channel Link  
LVDS video interface (4 LVDS Data + LVDS Clock)  
into a high-speed serialized interface over a single  
CML pair. The DS92LV042x enables applications  
currently using popular Channel Link or OpenLDI  
LVDS style devices to upgrade seamlessly to an  
embedded clock interface. This serial bus scheme  
reduces interconnect cost and eases design  
challenges. The parallel OpenLDI LVDS interface  
also reduces FPGA I/O pins, board trace count, and  
alleviates EMI issues when compared to traditional  
single-ended wide bus interfaces.  
1
5-Channel (4 Data + 1 Clock) Channel Link LVDS  
Parallel Interface Supports 24-Bit Data 3-Bit  
Control at 10 to 75 MHz  
AC-Coupled STP Interconnect Up to 10 m  
Integrated Terminations on Serializer and  
Deserializer  
At-Speed Link BIST Mode and Reporting Pin  
Optional I2C-Compatible Serial Control Bus  
Power-Down Mode Minimizes Power Dissipation  
1.8-V or 3.3-V Compatible LVCMOS I/O Interface  
>8-kV HBM  
Programmable  
transmit  
de-emphasis,  
receive  
equalization, on-chip scrambling, and DC-balancing  
enables longer distance transmission over lossy  
–40° to 85°C Temperature Range  
Serializer (DS92LV0421)  
cables  
and  
backplanes.  
The  
DS92LV0422  
Data Scrambler for Reduced EMI  
automatically locks to incoming data without an  
external reference clock or special sync patterns,  
providing easy plug-and-go operation.  
DC–Balance Encoder for AC Coupling  
Selectable Output VOD and Adjustable De-  
Emphasis  
The DS92LV042x chipset is programmable through  
an I2C interface as well as through pins. A built-in, at-  
speed BIST feature validates link integrity and may  
be used for system diagnostics. The DS92LV0421  
and DS92LV0422 can be used interchangeably with  
the DS92LV2421 or DS92LV2422. This allows  
designers the flexibility to connect to the host device  
and receiving devices with different interface types:  
LVDS or LVCMOS.  
Deserializer (DS92LV0422)  
Fast Random Data Lock; No Reference Clock  
Required  
Adjustable Input Receiver Equalization  
EMI Minimization on Output Parallel Bus  
(SSCG and LVDS VOD Select)  
Device Information(1)  
2 Applications  
Embedded Video and Displays  
PART NUMBER  
DS92LV0421  
PACKAGE  
WQFN (36)  
WQFN (48)  
BODY SIZE (NOM)  
6.00 mm × 6.00 mm  
7.00 mm × 7.00 mm  
Medical Imaging and Factory Automation  
Office Automation (Printers and Scanners)  
Security and Video Surveillance  
DS92LV0422  
(1) For all available packages, see the orderable addendum at  
the end of the data sheet.  
General-Purpose Data Communication  
Typical Application Block Diagram  
Channel Link  
Channel Link II  
Channel Link  
VDDIO  
(1.8V or 3.3V)  
VDDIO  
(1.8V or 3.3V)  
1.8V  
1.8V 3.3V  
RxIN3+/-  
RxIN2+/-  
TxOUT3+/-  
High-Speed Serial Link  
1 Pair/AC Coupled  
TxOUT2+/-  
Camera/AFE  
Or  
HOST  
Graphics  
Processor  
Frame Grabber  
Or  
RGB Display  
QVGA to XGA  
24-bit Color Depth  
DOUT+  
DOUT-  
RIN+  
RIN-  
RxIN1+/-  
RxIN0+/-  
TxOUT1+/-  
TxOUT0+/-  
100 ohm STP Cable  
RxCLKIN+/-  
TxCLKOUT+/-  
CMF  
DS92LV0421  
DS92LV0422  
LOCK  
PASS  
SSC[2:0]  
PDB  
BISTEN  
VODSEL  
De-Emph  
LFMODE  
MAPSEL  
CONFIG[1:0]  
CONFIG[1:0]  
PDB  
BISTEN  
MAPSEL  
OEN  
OSSEL  
VODSEL  
SCL  
SDA  
ID[x]  
SCL  
SDA  
ID[x]  
Optional  
Optional  
Copyright © 2016, Texas Instruments Incorporated  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 

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