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DS92LV0421SQE/NOPB PDF预览

DS92LV0421SQE/NOPB

更新时间: 2024-02-15 19:15:30
品牌 Logo 应用领域
德州仪器 - TI 驱动接口集成电路
页数 文件大小 规格书
58页 1257K
描述
具有 LVDS 并行接口的 10MHz 至 75MHz Channel-Link II 串行器 | NJK | 36 | -40 to 85

DS92LV0421SQE/NOPB 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:QFN
包装说明:LLP-36针数:36
Reach Compliance Code:compliantECCN代码:5A991.B.1
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:1.22Is Samacsys:N
差分输出:YES驱动器位数:24
输入特性:DIFFERENTIAL接口集成电路类型:LINE DRIVER
接口标准:I2CJESD-30 代码:S-XQCC-N36
JESD-609代码:e3长度:6 mm
湿度敏感等级:3功能数量:1
端子数量:36最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装等效代码:LCC36,.25SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260电源:1.8,3.3 V
认证状态:Not Qualified最大接收延迟:
座面最大高度:0.8 mm子类别:Line Driver or Receivers
最大压摆率:100 mA最大供电电压:1.89 V
最小供电电压:1.71 V标称供电电压:1.8 V
电源电压1-最大:1.89 V电源电压1-分钟:1.71 V
电源电压1-Nom:1.8 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:6 mmBase Number Matches:1

DS92LV0421SQE/NOPB 数据手册

 浏览型号DS92LV0421SQE/NOPB的Datasheet PDF文件第1页浏览型号DS92LV0421SQE/NOPB的Datasheet PDF文件第2页浏览型号DS92LV0421SQE/NOPB的Datasheet PDF文件第3页浏览型号DS92LV0421SQE/NOPB的Datasheet PDF文件第5页浏览型号DS92LV0421SQE/NOPB的Datasheet PDF文件第6页浏览型号DS92LV0421SQE/NOPB的Datasheet PDF文件第7页 
DS92LV0421, DS92LV0422  
SNLS325D MAY 2010REVISED DECEMBER 2016  
www.ti.com  
5 Pin Configuration and Functions  
NJK Package  
36-Pin WQFN  
Top View  
RXIN3œ  
RXIN3+  
RES6  
1
2
3
4
5
6
7
8
9
27  
26  
25  
24  
23  
22  
21  
20  
19  
RES4  
MAPSEL  
RES7  
ID[X]  
VDDRX  
PDB  
DAP  
VDDL  
SCL  
VDDIO  
BISTEN  
VODSEL  
DE-EMPH  
SDA  
RES0  
CONFIG[0]  
Not to scale  
Pin Functions: DS92LV0421  
PIN  
TYPE(1)  
DESCRIPTION(2)  
NAME  
NO.  
CHANNEL LINK PARALLEL INPUT INTERFACE  
True LVDS Clock Input  
This pair must have a 100-Ω termination for standard LVDS levels.  
RXCLKIN+  
RXCLKIN–  
RXIN[3:0]+  
RXIN[3:0]–  
35  
34  
I
I
I
I
Inverting LVDS Clock Input  
This pair must have a 100-Ω termination for standard LVDS levels.  
2, 33,  
31, 29  
True LVDS Data Input  
This pair must have a 100-Ω termination for standard LVDS levels.  
1, 32,  
30, 28  
Inverting LVDS Data Input  
This pair must have a 100-Ω termination for standard LVDS levels.  
CHANNEL LINK II SERIAL OUTPUT INTERFACE  
True Output, CML  
The output must be AC-coupled with a 0.1-µF capacitor.  
DOUT+  
DOUT–  
16  
15  
O
O
Inverting Output, CML  
The output must be AC-coupled with a 0.1-µF capacitor.  
(1) G = Ground, I = Input, O = Output, and P = Power  
(2) 1= HIGH, 0 = LOW  
4
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Copyright © 2010–2016, Texas Instruments Incorporated  
Product Folder Links: DS92LV0421 DS92LV0422  

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