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DS92LV090ATVEHX/NOPB PDF预览

DS92LV090ATVEHX/NOPB

更新时间： 2024-02-29 22:17:36
品牌 Logo 应用领域
德州仪器 - TI 驱动接口集成电路驱动器
页数 文件大小 规格书
19页 695K
描述
9 通道总线 LVDS 收发器 | PM | 64 | -40 to 85

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DS92LV090ATVEHX/NOPB 技术参数

是否Rohs认证： 符合生命周期：Transferred
包装说明：LFQFP, QFP64,.47SQ,20Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.38差分输出：YES
驱动器位数：9高电平输入电流最大值：0.00002 A
输入特性：DIFFERENTIAL接口集成电路类型：LINE TRANSCEIVER
接口标准：GENERAL PURPOSEJESD-30 代码：S-PQFP-G64
JESD-609代码：e3长度：10 mm
湿度敏感等级：3功能数量：9
端子数量：64最高工作温度：85 °C
最低工作温度：-40 °C最小输出摆幅：0.24 V
最大输出低电流：0.002 A封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装等效代码：QFP64,.47SQ,20
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified最大接收延迟：3.2 ns
接收器位数：9座面最大高度：1.6 mm
子类别：Line Driver or Receivers最大压摆率：210 mA
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：40最大传输延迟：2.2 ns
宽度：10 mmBase Number Matches：1

DS92LV090ATVEHX/NOPB 数据手册

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DS92LV090A  
www.ti.com  
SNLS025D –APRIL 2000–REVISED APRIL 2013  
DS92LV090A 9 Channel Bus LVDS Transceiver  
Check for Samples: DS92LV090A  
1
FEATURES  
DESCRIPTION  
The DS92LV090A is one in a series of Bus LVDS  
transceivers designed specifically for the high speed,  
low power proprietary backplane or cable interfaces.  
The device operates from a single 3.3V power supply  
and includes nine differential line drivers and nine  
receivers. To minimize bus loading, the driver outputs  
and receiver inputs are internally connected. The  
separate I/O of the logic side allows for loop back  
support. The device also features a flow through pin  
out which allows easy PCB routing for short stubs  
between its pins and the connector.  
2
•
•
•
•
•
Bus LVDS Signaling  
3.2 Nanosecond Propagation Delay Max  
Chip to Chip Skew ±800ps  
Low Power CMOS Design  
High Signaling Rate Capability (Above 100  
Mbps)  
•
0.1V to 2.3V Common Mode Range for VID  
200mV  
=
•
•
±100 mV Receiver Sensitivity  
The driver translates 3V TTL levels (single-ended) to  
differential Bus LVDS (BLVDS) output levels. This  
allows for high speed operation, while consuming  
minimal power with reduced EMI. In addition, the  
differential signaling provides common mode noise  
rejection of ±1V.  
Supports Open and Terminated Failsafe on  
Port Pins  
•
•
3.3V Operation  
Glitch Free Power Up/Down (Driver & Receiver  
Disabled)  
•
Light Bus Loading (5 pF Typical) per Bus  
LVDS Load  
The receiver threshold is less than ±100 mV over a  
±1V common mode range and translates the  
differential Bus LVDS to standard (TTL/CMOS)  
levels. (See Applications Information Section for more  
details.)  
•
•
•
•
Designed for Double Termination Applications  
Balanced Output Impedance  
Product Offered in 64 Pin LQFP Package  
High Impedance Bus Pins on Power off (VCC  
0V)  
=
•
•
Driver Channel to Channel Skew (Same  
Device) 230ps Typical  
Receiver Channel to Channel Skew (Same  
Device) 370ps Typical  
Simplified Functional Diagram  
Figure 1.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2000–2013, Texas Instruments Incorporated  
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