Datasheet > DS92LV0422SQX

DS92LV0422SQX

更新时间： 2024-11-16 06:54:43

品牌	Logo	应用领域
美国国家半导体 - NSC		/
页数	文件大小	规格书
40页	946K
描述
10 - 75 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface

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DS92LV0422SQX 数据手册

PRELIMINARY

May 26, 2010

DS92LV0421 / DS92LV0422

10 - 75 MHz Channel Link II Serializer/Deserializer with

LVDS Parallel Interface

General Description

Features

5-channel (4 data + 1 clock) Channel Link LVDS parallel

■

The DS92LV0421 (serializer) and DS92LV0422 (deserializer)

chipset translates a Channel Link LVDS video interface (4

LVDS Data + LVDS Clock) into a high-speed serialized inter-

face over a single CML pair.

interface supports 24-bit data 3-bit control at 10 – 75 MHz

AC Coupled STP Interconnect up to 10 meters in length

■

Integrated serial CML terminations

The DS92LV0421 and DS92LV0422 enable applications that

currently use the popular Channel Link or Channel Link style

devices to seamlessly upgrade to an embedded clock inter-

face to reduce interconnect cost or ease design challenges.

The parallel LVDS interface also reduces FPGA I/O pins,

board trace count and alleviates EMI issues, when compared

to traditional single-ended wide bus interfaces.

AT–SPEED BIST Mode and status pin

Optional I2C compatible Serial Control Bus

Power Down Mode minimizes power dissipation

1.8V or 3.3V compatible control pin interface

>8 kV ESD (HBM) protection

-40° to +85°C temperature range

Programmable transmit de-emphasis, receive equalization,

on-chip scrambling and DC balancing enables longer dis-

tance transmission over lossy cables and backplanes. The

Deserializer automatically locks to incoming data without an

external reference clock or special sync patterns, providing

easy “plug-and-go” operation.

SERIALIZER – DS92LV0421

Data scrambler for reduced EMI

■

DC–balance encoder for AC coupling

Selectable output VOD and adjustable de-emphasis

DESERIALIZER – DS92LV0422

The DS92LV0421 and DS92LV0422 are programmable

though an I2C interface as well as by pins. A built-in AT-

SPEED BIST feature validates link integrity and may be used

for system diagnostics.

Random data lock; no reference clock required

■

Adjustable input receiver equalization

EMI minimization on output parallel bus (Spread Spectrum

Clock Generation and LVDS VOD select)

The DS92LV0421 and DS92LV0422 can be used inter-

changeably with the DS92LV2421 or DS92LV2422. This al-

lows designers the flexibility to connect to the host device and

receiving devices with different interface types, LVDS or LVC-

MOS.

Applications

Embedded Video and Display

■

Machine Vision, Industrial Imaging, Medical Imaging

Office Automation — Printers, Scanners, Copiers

Security and Video Surveillance

General purpose data communication

■

Applications Diagram

30120927

TRI-STATE® is a registered trademark of National Semiconductor Corporation.

301209

www.national.com

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中文翻译

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与DS92LV0422SQX相关器件

型号	品牌	获取价格	描述	数据表
DS92LV0422SQX/NOPB	TI	获取价格	具有 LVDS 并行接口的 10 - 75MHz Channel Link II 解串器
DS92LV090A	NSC	获取价格	9 Channel Bus LVDS Transceiver
DS92LV090A	TI	获取价格	9 通道总线 LVDS 收发器
DS92LV090A_07	NSC	获取价格	9 Channel Bus LVDS Transceiver
DS92LV090AEP	TI	获取价格	DS92LV090AEP 9 Channel Bus LVDS Transceiver
DS92LV090ATCEH	ETC	获取价格	Transceiver
DS92LV090ATVEH	NSC	获取价格	9 Channel Bus LVDS Transceiver
DS92LV090ATVEH/NOPB	TI	获取价格	9 通道总线 LVDS 收发器 \| PM \| 64 \| -40 to 85
DS92LV090ATVEHX	NSC	获取价格	暂无描述
DS92LV090ATVEHX/NOPB	TI	获取价格	9 通道总线 LVDS 收发器 \| PM \| 64 \| -40 to 85

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