DS90LV110AT

更新时间： 2024-09-26 22:50:51

品牌	Logo	应用领域
美国国家半导体 - NSC		时钟
页数	文件大小	规格书
9页	390K
描述
1 to 10 LVDS Data/Clock Distributor with Failsafe

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DS90LV110AT 数据手册

October 2004

DS90LV110AT

1 to 10 LVDS Data/Clock Distributor with Failsafe

General Description

Features

n Low jitter 400 Mbps fully differential data path

n 145 ps (typ) of pk-pk jitter with PRBS = 2²³−1 data

pattern at 400 Mbps

DS90LV110A is a 1 to 10 data/clock distributor utilizing LVDS

(Low Voltage Differential Signaling) technology for low

power, high speed operation. Data paths are fully differential

from input to output for low noise generation and low pulse

width distortion. The design allows connection of 1 input to

all 10 outputs. LVDS I/O enable high speed data transmis-

sion for point-to-point interconnects. This device can be used

as a high speed differential 1 to 10 signal distribution / fanout

replacing multi-drop bus applications for higher speed links

with improved signal quality. It can also be used for clock

distribution up to 200MHz.

n Single +3.3 V Supply

n Balanced output impedance

n Output channel-to-channel skew is 35ps (typ)

n Differential output voltage (V_OD) is 320mV (typ) with

100Ω termination load.

n LVDS receiver inputs accept LVPECL signals

n LVDS input failsafe

n Fast propagation delay of 2.8 ns (typ)

n Receiver open, shorted, and terminated input failsafe

n 28 lead TSSOP package

The DS90LV110A accepts LVDS signal levels, LVPECL lev-

els directly or PECL with attenuation networks.

The LVDS outputs can be put into TRI-STATE by use of the

enable pin.

n Conforms to ANSI/TIA/EIA-644 LVDS standard

For more details, please refer to the Application Information

section of this datasheet.

Connection Diagram

Block Diagram

20098201

20098205

Order Number DS90LV110ATMT

See NS Package Number MTC28

DS200982

www.national.com

12 3 4 5 6 7...9

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与DS90LV110AT相关器件

型号	品牌	获取价格	描述	数据表
DS90LV110AT_07	NSC	获取价格	1 to 10 LVDS Data/Clock Distributor with Failsafe
DS90LV110AT_08	NSC	获取价格	1 to 10 LVDS Data/Clock Distributor with Failsafe
DS90LV110ATMT	TI	获取价格	具有失效防护的 1:10 LVDS 数据/时钟分配器 \| PW \| 28 \| -40 to
DS90LV110ATMT	NSC	获取价格	1 to 10 LVDS Data/Clock Distributor with Failsafe
DS90LV110ATMT/NOPB	TI	获取价格	具有失效防护的 1:10 LVDS 数据/时钟分配器 \| PW \| 28 \| -40 to
DS90LV110ATMTX	NSC	获取价格	IC 90LV SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28, TS
DS90LV110ATMTX/NOPB	TI	获取价格	具有失效防护的 1:10 LVDS 数据/时钟分配器 \| PW \| 28 \| -40 to
DS90LV110T	NSC	获取价格	1 to 10 LVDS Data/Clock Distributor
DS90LV110T	TI	获取价格	1:10 LVDS 数据/时钟分配器
DS90LV110T_07	NSC	获取价格	1 to 10 LVDS Data/Clock Distributor